ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macro

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / GicV3 / AArch64 / ArmGicV3.S

#\r
#  Copyright (c) 2014, ARM Limited. All rights reserved.\r
#\r
#  This program and the accompanying materials are licensed and made available\r
#  under the terms and conditions of the BSD License which accompanies this\r
#  distribution. The full text of the license may be found at\r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#\r
\r
#include <AsmMacroIoLibV8.h>\r
\r
#if !defined(__clang__)\r
\r
//\r
// Clang versions before v3.6 do not support the GNU extension that allows\r
// system registers outside of the IMPLEMENTATION DEFINED range to be specified\r
// using the generic notation below. However, clang knows these registers by\r
// their architectural names, so it has no need for these aliases anyway.\r
//\r
#define ICC_SRE_EL1             S3_0_C12_C12_5\r
#define ICC_SRE_EL2             S3_4_C12_C9_5\r
#define ICC_SRE_EL3             S3_6_C12_C12_5\r
#define ICC_IGRPEN1_EL1         S3_0_C12_C12_7\r
#define ICC_EOIR1_EL1           S3_0_C12_C12_1\r
#define ICC_IAR1_EL1            S3_0_C12_C12_0\r
#define ICC_PMR_EL1             S3_0_C4_C6_0\r
#define ICC_BPR1_EL1            S3_0_C12_C12_3\r
\r
#endif\r
\r
//UINT32\r
//EFIAPI\r
//ArmGicV3GetControlSystemRegisterEnable (\r
//  VOID\r
//  );\r
ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable)\r
        EL1_OR_EL2_OR_EL3(x1)\r
1:  mrs x0, ICC_SRE_EL1\r
        b       4f\r
2:  mrs x0, ICC_SRE_EL2\r
        b       4f\r
3:  mrs x0, ICC_SRE_EL3\r
4:  ret\r
\r
//VOID\r
//EFIAPI\r
//ArmGicV3SetControlSystemRegisterEnable (\r
//  IN UINT32         ControlSystemRegisterEnable\r
//  );\r
ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)\r
        EL1_OR_EL2_OR_EL3(x1)\r
1:  msr ICC_SRE_EL1, x0\r
        b       4f\r
2:  msr ICC_SRE_EL2, x0\r
        b       4f\r
3:  msr ICC_SRE_EL3, x0\r
4:  isb\r
        ret\r
\r
//VOID\r
//ArmGicV3EnableInterruptInterface (\r
//  VOID\r
//  );\r
ASM_FUNC(ArmGicV3EnableInterruptInterface)\r
        mov     x0, #1\r
        msr     ICC_IGRPEN1_EL1, x0\r
        ret\r
\r
//VOID\r
//ArmGicV3DisableInterruptInterface (\r
//  VOID\r
//  );\r
ASM_FUNC(ArmGicV3DisableInterruptInterface)\r
        mov     x0, #0\r
        msr     ICC_IGRPEN1_EL1, x0\r
        ret\r
\r
//VOID\r
//ArmGicV3EndOfInterrupt (\r
//  IN UINTN          InterruptId\r
//  );\r
ASM_FUNC(ArmGicV3EndOfInterrupt)\r
        msr     ICC_EOIR1_EL1, x0\r
        ret\r
\r
//UINTN\r
//ArmGicV3AcknowledgeInterrupt (\r
//  VOID\r
//  );\r
ASM_FUNC(ArmGicV3AcknowledgeInterrupt)\r
        mrs     x0, ICC_IAR1_EL1\r
        ret\r
\r
//VOID\r
//ArmGicV3SetPriorityMask (\r
//  IN UINTN          Priority\r
//  );\r
ASM_FUNC(ArmGicV3SetPriorityMask)\r
        msr     ICC_PMR_EL1, x0\r
        ret\r
\r
//VOID\r
//ArmGicV3SetBinaryPointer (\r
//  IN UINTN          BinaryPoint\r
//  );\r
ASM_FUNC(ArmGicV3SetBinaryPointer)\r
        msr     ICC_BPR1_EL1, x0\r
        ret\r