projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| d7133859 OM |
1 | //\r |
| 2 | // Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
| 3 | //\r | |
| 4 | // This program and the accompanying materials are licensed and made available\r | |
| 5 | // under the terms and conditions of the BSD License which accompanies this\r | |
| 6 | // distribution. The full text of the license may be found at\r | |
| 7 | // http://opensource.org/licenses/bsd-license.php\r | |
| 8 | //\r | |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | //\r | |
| 12 | //\r | |
| 13 | \r | |
| 14 | // For the moment we assume this will run in SVC mode on ARMv7\r | |
| 15 | \r | |
| 5f81082e OM |
16 | EXPORT ArmGicV3GetControlSystemRegisterEnable\r |
| 17 | EXPORT ArmGicV3SetControlSystemRegisterEnable\r | |
| d7133859 OM |
18 | EXPORT ArmGicV3EnableInterruptInterface\r |
| 19 | EXPORT ArmGicV3DisableInterruptInterface\r | |
| 20 | EXPORT ArmGicV3EndOfInterrupt\r | |
| 21 | EXPORT ArmGicV3AcknowledgeInterrupt\r | |
| 22 | EXPORT ArmGicV3SetPriorityMask\r | |
| 23 | EXPORT ArmGicV3SetBinaryPointer\r | |
| 24 | \r | |
| 25 | AREA ArmGicV3, CODE, READONLY\r | |
| 26 | \r | |
| 27 | //UINT32\r | |
| 28 | //EFIAPI\r | |
| 29 | //ArmGicGetControlSystemRegisterEnable (\r | |
| 30 | // VOID\r | |
| 31 | // );\r | |
| 5f81082e | 32 | ArmGicV3GetControlSystemRegisterEnable\r |
| d7133859 OM |
33 | mrc p15, 0, r0, c12, c12, 5 // ICC_SRE\r |
| 34 | bx lr\r | |
| 35 | \r | |
| 36 | //VOID\r | |
| 37 | //EFIAPI\r | |
| 38 | //ArmGicSetControlSystemRegisterEnable (\r | |
| 39 | // IN UINT32 ControlSystemRegisterEnable\r | |
| 40 | // );\r | |
| 5f81082e | 41 | ArmGicV3SetControlSystemRegisterEnable\r |
| d7133859 OM |
42 | mcr p15, 0, r0, c12, c12, 5 // ICC_SRE\r |
| 43 | isb\r | |
| 44 | bx lr\r | |
| 45 | \r | |
| 46 | //VOID\r | |
| 47 | //ArmGicV3EnableInterruptInterface (\r | |
| 48 | // VOID\r | |
| 49 | // );\r | |
| 50 | ArmGicV3EnableInterruptInterface\r | |
| 51 | mov r0, #1\r | |
| 52 | mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r | |
| 53 | bx lr\r | |
| 54 | \r | |
| 55 | //VOID\r | |
| 56 | //ArmGicV3DisableInterruptInterface (\r | |
| 57 | // VOID\r | |
| 58 | // );\r | |
| 59 | ArmGicV3DisableInterruptInterface\r | |
| 60 | mov r0, #0\r | |
| 61 | mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r | |
| 62 | bx lr\r | |
| 63 | \r | |
| 64 | //VOID\r | |
| 65 | //ArmGicV3EndOfInterrupt (\r | |
| 66 | // IN UINTN InterruptId\r | |
| 67 | // );\r | |
| 68 | ArmGicV3EndOfInterrupt\r | |
| 69 | mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r | |
| 70 | bx lr\r | |
| 71 | \r | |
| 72 | //UINTN\r | |
| 73 | //ArmGicV3AcknowledgeInterrupt (\r | |
| 74 | // VOID\r | |
| 75 | // );\r | |
| 76 | ArmGicV3AcknowledgeInterrupt\r | |
| 77 | mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1\r | |
| 78 | bx lr\r | |
| 79 | \r | |
| 80 | //VOID\r | |
| 81 | //ArmGicV3SetPriorityMask (\r | |
| 82 | // IN UINTN Priority\r | |
| 83 | // );\r | |
| 84 | ArmGicV3SetPriorityMask\r | |
| 85 | mcr p15, 0, r0, c4, c6, 0 //ICC_PMR\r | |
| 86 | bx lr\r | |
| 87 | \r | |
| 88 | //VOID\r | |
| 89 | //ArmGicV3SetBinaryPointer (\r | |
| 90 | // IN UINTN BinaryPoint\r | |
| 91 | // );\r | |
| 92 | ArmGicV3SetBinaryPointer\r | |
| 93 | mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1\r | |
| 94 | bx lr\r | |
| 95 | \r | |
| 96 | END\r |