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d7133859 OM |
1 | /** @file\r |
2 | *\r | |
41fb5d46 | 3 | * Copyright (c) 2014-2015, ARM Limited. All rights reserved.\r |
d7133859 OM |
4 | *\r |
5 | * This program and the accompanying materials are licensed and made available\r | |
6 | * under the terms and conditions of the BSD License which accompanies this\r | |
7 | * distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _ARM_GIC_V3_H_\r | |
16 | #define _ARM_GIC_V3_H_\r | |
17 | \r | |
5f81082e OM |
18 | #define ICC_SRE_EL2_SRE (1 << 0)\r |
19 | \r | |
41fb5d46 OM |
20 | #define ARM_GICD_IROUTER_IRM BIT31\r |
21 | \r | |
5f81082e OM |
22 | UINT32\r |
23 | EFIAPI\r | |
24 | ArmGicV3GetControlSystemRegisterEnable (\r | |
25 | VOID\r | |
26 | );\r | |
27 | \r | |
28 | VOID\r | |
29 | EFIAPI\r | |
30 | ArmGicV3SetControlSystemRegisterEnable (\r | |
31 | IN UINT32 ControlSystemRegisterEnable\r | |
32 | );\r | |
33 | \r | |
d7133859 OM |
34 | VOID\r |
35 | EFIAPI\r | |
36 | ArmGicV3EnableInterruptInterface (\r | |
37 | VOID\r | |
38 | );\r | |
39 | \r | |
40 | VOID\r | |
41 | EFIAPI\r | |
42 | ArmGicV3DisableInterruptInterface (\r | |
43 | VOID\r | |
44 | );\r | |
45 | \r | |
46 | UINTN\r | |
47 | EFIAPI\r | |
48 | ArmGicV3AcknowledgeInterrupt (\r | |
49 | VOID\r | |
50 | );\r | |
51 | \r | |
52 | VOID\r | |
53 | EFIAPI\r | |
54 | ArmGicV3EndOfInterrupt (\r | |
55 | IN UINTN Source\r | |
56 | );\r | |
57 | \r | |
58 | VOID\r | |
59 | ArmGicV3SetBinaryPointer (\r | |
60 | IN UINTN BinaryPoint\r | |
61 | );\r | |
62 | \r | |
63 | VOID\r | |
64 | ArmGicV3SetPriorityMask (\r | |
65 | IN UINTN Priority\r | |
66 | );\r | |
67 | \r | |
68 | #endif\r |