Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...
[mirror_edk2.git] / ArmPkg / Drivers / PL35xSmc / InitializeSMC.S
CommitLineData
1bfda055 1#\r
2# Copyright (c) 2011, ARM Limited. All rights reserved.\r
3# \r
4# This program and the accompanying materials \r
5# are licensed and made available under the terms and conditions of the BSD License \r
6# which accompanies this distribution. The full text of the license may be found at \r
7# http:#opensource.org/licenses/bsd-license.php \r
8#\r
9# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11#\r
12#\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Library/PcdLib.h>\r
16#include <AutoGen.h>\r
17#include <AsmMacroIoLib.h>\r
18\r
19#Start of the code section\r
20.text\r
21\r
22#Maintain 8 byte alignment\r
23.align 3\r
24\r
25#Export Initialize SMC symbol\r
26GCC_ASM_EXPORT(InitializeSMC)\r
27\r
28# Static memory configuation definitions for SMC\r
29.set SmcDirectCmd, 0x10\r
30.set SmcSetCycles, 0x14\r
31.set SmcSetOpMode, 0x18\r
32\r
33# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
34# CS1 CS1-Interf0 Reserved for the motherboard\r
35# CS2 CS2-Interf0 SRAM on the motherboard\r
36# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
37# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
38# CS5 CS1-Interf1 memory-mapped peripherals\r
39# CS6 CS2-Interf1 memory-mapped peripherals\r
40# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
41\r
42# IN r1 SmcBase\r
43# IN r2 VideoSRamBase\r
44# NOTE: This code is been called before any stack has been setup. It means some registers\r
45# could be overwritten (case of 'r0')\r
46\r
47\r
48ASM_PFX(InitializeSMC):\r
49#\r
50# Setup NOR1 (CS0-Interface0)\r
51#\r
52\r
53 #Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
54 #Read cycle timeout = 0xA (0:3)\r
55 #Write cycle timeout = 0x3(7:4)\r
56 #OE Assertion Delay = 0x9(11:8)\r
57 #WE Assertion delay = 0x3(15:12)\r
58 #Page cycle timeout = 0x2(19:16) \r
59 LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
60 str r0, [r1, #SmcSetCycles]\r
61 \r
62 #Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
63 # 0x00000002 = MemoryWidth: 32bit\r
64 # 0x00000028 = ReadMemoryBurstLength:continuous\r
65 # 0x00000280 = WriteMemoryBurstLength:continuous\r
66 # 0x00000800 = Set Address Valid\r
67 LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
68 str r0, [r1, #SmcSetOpMode] \r
69\r
70 #Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
71 # 0x00000000 = ChipSelect0-Interface 0\r
72 # 0x00400000 = CmdTypes: UpdateRegs\r
73 LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
74 str r0, [r1, #SmcDirectCmd] \r
75 \r
76 \r
77#\r
78# Setup SRAM (CS2-Interface0)\r
79#\r
80 LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
81 str r0, [r1, #SmcSetCycles]\r
82\r
83 # 0x00000002 = MemoryWidth: 32bit\r
84 # 0x00000800 = Set Address Valid\r
85 LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
86 str r0, [r1, #SmcSetOpMode]\r
87 \r
88 # 0x01000000 = ChipSelect2-Interface 0\r
89 # 0x00400000 = CmdTypes: UpdateRegs\r
90 LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
91 str r0, [r1, #SmcDirectCmd]\r
92\r
93#\r
94# USB/Eth/VRAM (CS3-Interface0)\r
95#\r
96 LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
97 str r0, [r1, #SmcSetCycles]\r
98 \r
99 # 0x00000002 = MemoryWidth: 32bit\r
100 # 0x00000004 = Memory reads are synchronous\r
101 # 0x00000040 = Memory writes are synchronous\r
102 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
103 str r0, [r1, #SmcSetOpMode] \r
104 \r
105 # 0x01800000 = ChipSelect3-Interface 0\r
106 # 0x00400000 = CmdTypes: UpdateRegs\r
107 LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
108 str r0, [r1, #SmcDirectCmd] \r
109\r
110#\r
111# Setup NOR3 (CS0-Interface1)\r
112#\r
113 LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
114 str r0, [r1, #SmcSetCycles]\r
115 \r
116 # 0x00000002 = MemoryWidth: 32bit\r
117 # 0x00000028 = ReadMemoryBurstLength:continuous\r
118 # 0x00000280 = WriteMemoryBurstLength:continuous\r
119 # 0x00000800 = Set Address Valid\r
120 LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
121 str r0, [r1, #SmcSetOpMode] \r
122 \r
123 # 0x02000000 = ChipSelect0-Interface 1\r
124 # 0x00400000 = CmdTypes: UpdateRegs\r
125 LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
126 str r0, [r1, #SmcDirectCmd] \r
127 \r
128#\r
129# Setup Peripherals (CS3-Interface1)\r
130#\r
131 LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
132 str r0, [r1, #SmcSetCycles]\r
133 \r
134 # 0x00000002 = MemoryWidth: 32bit\r
135 # 0x00000004 = Memory reads are synchronous\r
136 # 0x00000040 = Memory writes are synchronous\r
137 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
138 str r0, [r1, #SmcSetOpMode] \r
139 \r
140 # 0x03800000 = ChipSelect3-Interface 1\r
141 # 0x00400000 = CmdTypes: UpdateRegs\r
142 LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
143 str r0, [r1, #SmcDirectCmd] \r
144\r
145#\r
146# Setup VRAM (CS1-Interface0)\r
147#\r
148 LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
149 str r0, [r1, #SmcSetCycles]\r
150 \r
151 # 0x00000002 = MemoryWidth: 32bit\r
152 # 0x00000004 = Memory reads are synchronous\r
153 # 0x00000040 = Memory writes are synchronous\r
154 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
155 str r0, [r1, #SmcSetOpMode] \r
156 \r
157 # 0x00800000 = ChipSelect1-Interface 0\r
158 # 0x00400000 = CmdTypes: UpdateRegs\r
159 LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
160 str r0, [r1, #SmcDirectCmd] \r
161 \r
162#\r
163# Page mode setup for VRAM\r
164#\r
165 #read current state \r
166 ldr r0, [r2, #0] \r
167 ldr r0, [r2, #0] \r
168 LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
169 str r0, [r2, #0] \r
170 ldr r0, [r2, #0] \r
171\r
172 #enable page mode \r
173 ldr r0, [r2, #0] \r
174 ldr r0, [r2, #0] \r
175 LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
176 str r0, [r2, #0] \r
177 LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
178 str r0, [r2, #0] \r
179\r
180 #confirm page mode enabled\r
181 ldr r0, [r2, #0] \r
182 ldr r0, [r2, #0] \r
183 LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
184 str r0, [r2, #0] \r
185 ldr r0, [r2, #0] \r
186 \r
187 bx lr\r
188 \r
189ASM_FUNCTION_REMOVE_IF_UNREFERENCED