ArmPkg/PL35xSmc: Split the SMC initialization in multiple Chip Select initialization...

[mirror_edk2.git] / ArmPkg / Drivers / PL35xSmc / InitializeSMC.asm

//\r
//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
//  \r
//  This program and the accompanying materials                          \r
//  are licensed and made available under the terms and conditions of the BSD License         \r
//  which accompanies this distribution.  The full text of the license may be found at        \r
//  http://opensource.org/licenses/bsd-license.php                                            \r
//\r
//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Drivers/PL354Smc.h>\r
#include <AutoGen.h>\r
\r
  INCLUDE AsmMacroIoLib.inc\r
  \r
  EXPORT  SMCInitializeNOR\r
  EXPORT  SMCInitializeSRAM\r
  EXPORT  SMCInitializePeripherals\r
  EXPORT  SMCInitializeVRAM\r
\r
  PRESERVE8\r
  AREA    ModuleInitializeSMC, CODE, READONLY\r
  \r
// CS0  CS0-Interf0     NOR1 flash on the motherboard\r
// CS1  CS1-Interf0     Reserved for the motherboard\r
// CS2  CS2-Interf0     SRAM on the motherboard\r
// CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard\r
// CS4  CS0-Interf1     NOR2 flash on the motherboard\r
// CS5  CS1-Interf1     memory-mapped peripherals\r
// CS6  CS2-Interf1     memory-mapped peripherals\r
// CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.\r
\r
// IN r1 SmcBase\r
// IN r2 ChipSelect\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
SMCInitializeNOR\r
  // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
  //   - Read cycle timeout  = 0xA (0:3)\r
  //   - Write cycle timeout = 0x3(7:4)\r
  //   - OE Assertion Delay  = 0x9(11:8)\r
  //   - WE Assertion delay  = 0x3(15:12)\r
  //   - Page cycle timeout  = 0x2(19:16)\r
  ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
  // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
  ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
  // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
  ldr     r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
  orr     r0, r0, r2\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  bx    lr\r
\r
\r
//\r
// Setup SRAM (CS2-Interface0)\r
//\r
SMCInitializeSRAM\r
  ldr     r0, = 0x00027158\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
  \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
SMCInitializePeripherals\r
//\r
// USB/Eth/VRAM (CS3-Interface0)\r
//\r
  ldr     r0, = 0x000CD2AA\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
\r
//\r
// Setup Peripherals (CS3-Interface1)\r
//\r
  ldr     r0, = 0x00025156\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
\r
// IN r1 SmcBase\r
// IN r2 VideoSRamBase\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
SMCInitializeVRAM\r
  //\r
  // Setup VRAM (CS1-Interface0)\r
  //\r
  ldr     r0, =  0x00049249\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  ldr     r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  ldr     r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  //\r
  // Page mode setup for VRAM\r
  //\r
\r
  // Read current state\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
\r
  // Enable page mode\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, = 0x00900090\r
  str     r0, [r2, #0] \r
\r
  // Confirm page mode enabled\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
  \r
  bx    lr\r
  \r
  END\r