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1 | /** @file\r |
| 2 | *\r |
| 3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 4 | * \r |
| 5 | * This program and the accompanying materials \r |
| 6 | * are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | * which accompanies this distribution. The full text of the license may be found at \r |
| 8 | * http://opensource.org/licenses/bsd-license.php \r |
| 9 | *\r |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 12 | *\r |
| 13 | **/\r |
| 14 | \r |
| 15 | #include <Uefi.h>\r |
| 16 | #include <Library/IoLib.h>\r |
| 17 | #include <Library/ArmGicLib.h>\r |
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18 | #include <Library/PcdLib.h>\r |
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19 | \r |
| 20 | VOID\r |
| 21 | EFIAPI\r |
| 22 | ArmGicSendSgiTo (\r |
| 23 | IN INTN GicDistributorBase,\r |
| 24 | IN INTN TargetListFilter,\r |
| 25 | IN INTN CPUTargetList\r |
| 26 | )\r |
| 27 | {\r |
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28 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | PcdGet32(PcdGicSgiIntId));\r |
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29 | }\r |
| 30 | \r |
| 31 | UINT32\r |
| 32 | EFIAPI\r |
| 33 | ArmGicAcknowledgeSgiFrom (\r |
| 34 | IN INTN GicInterruptInterfaceBase,\r |
| 35 | IN INTN CoreId\r |
| 36 | )\r |
| 37 | {\r |
| 38 | INTN InterruptId;\r |
| 39 | \r |
| 40 | InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
| 41 | \r |
| 42 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
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43 | if ((((CoreId & 0x7) << 10) | PcdGet32(PcdGicSgiIntId)) == InterruptId) {\r |
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44 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
| 45 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r |
| 46 | return 1;\r |
| 47 | } else {\r |
| 48 | return 0;\r |
| 49 | }\r |
| 50 | }\r |
| 51 | \r |
| 52 | UINT32\r |
| 53 | EFIAPI\r |
| 54 | ArmGicAcknowledgeSgi2From (\r |
| 55 | IN INTN GicInterruptInterfaceBase,\r |
| 56 | IN INTN CoreId,\r |
| 57 | IN INTN SgiId\r |
| 58 | )\r |
| 59 | {\r |
| 60 | INTN InterruptId;\r |
| 61 | \r |
| 62 | InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
| 63 | \r |
| 64 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
| 65 | if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r |
| 66 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
| 67 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r |
| 68 | return 1;\r |
| 69 | } else {\r |
| 70 | return 0;\r |
| 71 | }\r |
| 72 | }\r |
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