ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC CPU ID...

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicDxe.c

/*++\r
\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r
\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   \r
\r
Module Name:\r
\r
  Gic.c\r
\r
Abstract:\r
\r
  Driver implementing the GIC interrupt controller protocol\r
\r
--*/\r
\r
#include <PiDxe.h>\r
\r
#include <Library/ArmLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
#include <Protocol/Cpu.h>\r
#include <Protocol/HardwareInterrupt.h>\r
\r
#define ARM_GIC_DEFAULT_PRIORITY  0x80\r
\r
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
\r
//\r
// Notifications\r
//\r
EFI_EVENT EfiExitBootServicesEvent      = (EFI_EVENT)NULL;\r
\r
// Maximum Number of Interrupts\r
UINTN mGicNumInterrupts                 = 0;\r
\r
HARDWARE_INTERRUPT_HANDLER  *gRegisteredInterruptHandlers = NULL;\r
\r
/**\r
  Register Handler for the specified interrupt source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
  @param Handler  Callback for interrupt. NULL to unregister\r
\r
  @retval EFI_SUCCESS Source was updated to support Handler.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RegisterInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
  IN HARDWARE_INTERRUPT_HANDLER         Handler\r
  )\r
{\r
  if (Source > mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
  \r
  if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
    return EFI_ALREADY_STARTED;\r
  }\r
\r
  gRegisteredInterruptHandlers[Source] = Handler;\r
\r
  // If the interrupt handler is unregistered then disable the interrupt\r
  if (NULL == Handler){\r
  	return This->DisableInterruptSource (This, Source);\r
  } else {\r
  	return This->EnableInterruptSource (This, Source);\r
  }\r
}\r
\r
/**\r
  Enable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt enabled.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EnableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
  \r
  if (Source > mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
  \r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write set-enable register\r
  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r
  \r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Disable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt disabled.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
  \r
  if (Source > mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
  \r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write set-enable register\r
  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r
  \r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Return current state of interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
  @param InterruptState  TRUE: source enabled, FALSE: source disabled.\r
\r
  @retval EFI_SUCCESS       InterruptState is valid\r
  @retval EFI_DEVICE_ERROR  InterruptState is not valid\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetInterruptSourceState (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
  IN BOOLEAN                            *InterruptState\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
  \r
  if (Source > mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
  \r
  // calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
    \r
  if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r
    *InterruptState = FALSE;\r
  } else {\r
    *InterruptState = TRUE;\r
  }\r
  \r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Signal to the hardware that the End Of Intrrupt state \r
  has been reached.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt EOI'ed.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EndOfInterrupt (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  if (Source > mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
\r
  @return None\r
\r
**/\r
VOID\r
EFIAPI\r
IrqInterruptHandler (\r
  IN EFI_EXCEPTION_TYPE           InterruptType,\r
  IN EFI_SYSTEM_CONTEXT           SystemContext\r
  )\r
{\r
  UINT32                      GicInterrupt;\r
  HARDWARE_INTERRUPT_HANDLER  InterruptHandler;\r
\r
  GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r
\r
  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
  if (GicInterrupt >= mGicNumInterrupts) {\r
    // The special interrupt do not need to be acknowledge\r
    return;\r
  }\r
  \r
  InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
  if (InterruptHandler != NULL) {\r
    // Call the registered interrupt handler.\r
    InterruptHandler (GicInterrupt, SystemContext);\r
  } else {\r
    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
  }\r
\r
  EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
}\r
\r
//\r
// Making this global saves a few bytes in image size\r
//\r
EFI_HANDLE  gHardwareInterruptHandle = NULL;\r
\r
//\r
// The protocol instance produced by this driver\r
//\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
  RegisterInterruptSource,\r
  EnableInterruptSource,\r
  DisableInterruptSource,\r
  GetInterruptSourceState,\r
  EndOfInterrupt\r
};\r
\r
/**\r
  Shutdown our hardware\r
  \r
  DXE Core will disable interrupts and turn off the timer and disable interrupts\r
  after all the event handlers have run.\r
\r
  @param[in]  Event   The Event that is being processed\r
  @param[in]  Context Event Context\r
**/\r
VOID\r
EFIAPI\r
ExitBootServicesEvent (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  UINTN    Index;\r
  \r
  // Acknowledge all pending interrupts\r
  for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
    DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
  }\r
\r
  for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
    EndOfInterrupt (&gHardwareInterruptProtocol, Index);\r
  }\r
\r
  // Disable Gic Interface\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r
\r
  // Disable Gic Distributor\r
  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r
}\r
\r
/**\r
  Initialize the state information for the CPU Architectural Protocol\r
\r
  @param  ImageHandle   of the loaded driver\r
  @param  SystemTable   Pointer to the System Table\r
\r
  @retval EFI_SUCCESS           Protocol registered\r
  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure\r
  @retval EFI_DEVICE_ERROR      Hardware problems\r
\r
**/\r
EFI_STATUS\r
InterruptDxeInitialize (\r
  IN EFI_HANDLE         ImageHandle,\r
  IN EFI_SYSTEM_TABLE   *SystemTable\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINTN                   Index;\r
  UINT32                  RegOffset;\r
  UINTN                   RegShift;\r
  EFI_CPU_ARCH_PROTOCOL   *Cpu;\r
  UINT32                  CpuTarget;\r
  \r
  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
  DEBUG_CODE_BEGIN();\r
  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
  }\r
  DEBUG_CODE_END();\r
\r
  // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
  mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));\r
\r
  for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
    DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
    \r
    // Set Priority \r
    RegOffset = Index / 4;\r
    RegShift = (Index % 4) * 8;\r
    MmioAndThenOr32 (\r
      PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),\r
      ~(0xff << RegShift), \r
      ARM_GIC_DEFAULT_PRIORITY << RegShift\r
      );\r
  }\r
\r
  //\r
  // Targets the interrupts to the Primary Cpu\r
  //\r
\r
  // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
  // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
  // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
  // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
  //\r
  // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
  // first SGIs)\r
  CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
\r
  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
  // cannot be 0.\r
  ASSERT (CpuTarget != 0);\r
\r
  // The 8 first Interrupt Processor Targets Registers are read-only\r
  for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
    MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
  }\r
\r
  // Set binary point reg to 0x7 (no preemption)\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);\r
\r
  // Set priority mask reg to 0xff to allow all priorities through\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
  \r
  // Enable gic cpu interface\r
  MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r
\r
  // Enable gic distributor\r
  MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r
  \r
  // Initialize the array for the Interrupt Handlers\r
  gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
  \r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                  &gHardwareInterruptHandle,\r
                  &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r
                  NULL\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
  \r
  //\r
  // Get the CPU protocol that this driver requires.\r
  //\r
  Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // Unregister the default exception handler.\r
  //\r
  Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // Register to receive interrupts\r
  //\r
  Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  // Register for an ExitBootServicesEvent\r
  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r