MdeMdeModulePkg/Scsi: Enlarge SCSI cmd timeout to a more reasonable experience value...

[mirror_edk2.git] / ArmPkg / Include / Chipset / AArch64.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __AARCH64_H__\r
#define __AARCH64_H__\r
\r
#include <Chipset/AArch64Mmu.h>\r
#include <Chipset/ArmArchTimer.h>\r
\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_AARCH64_IRQ\r
\r
// CPACR - Coprocessor Access Control Register definitions\r
#define CPACR_TTA_EN            (1UL << 28)\r
#define CPACR_FPEN_EL1          (1UL << 20)\r
#define CPACR_FPEN_FULL         (3UL << 20)\r
#define CPACR_CP_FULL_ACCESS    0x300000\r
\r
// Coprocessor Trap Register (CPTR)\r
#define AARCH64_CPTR_TFP        (1 << 10)\r
\r
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r
#define AARCH64_PFR0_FP         (0xF << 16)\r
\r
// NSACR - Non-Secure Access Control Register definitions\r
#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)\r
#define NSACR_NSD32DIS          (1 << 14)\r
#define NSACR_NSASEDIS          (1 << 15)\r
#define NSACR_PLE               (1 << 16)\r
#define NSACR_TL                (1 << 17)\r
#define NSACR_NS_SMP            (1 << 18)\r
#define NSACR_RFR               (1 << 19)\r
\r
// SCR - Secure Configuration Register definitions\r
#define SCR_NS                  (1 << 0)\r
#define SCR_IRQ                 (1 << 1)\r
#define SCR_FIQ                 (1 << 2)\r
#define SCR_EA                  (1 << 3)\r
#define SCR_FW                  (1 << 4)\r
#define SCR_AW                  (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
#define ARM_CPU_TYPE_MASK       0xFFF\r
#define ARM_CPU_TYPE_AEMv8      0xD0F\r
#define ARM_CPU_TYPE_A15        0xC0F\r
#define ARM_CPU_TYPE_A9         0xC09\r
#define ARM_CPU_TYPE_A5         0xC05\r
\r
// Hypervisor Configuration Register\r
#define ARM_HCR_FMO				BIT3\r
#define ARM_HCR_IMO				BIT4\r
#define ARM_HCR_AMO				BIT5\r
#define ARM_HCR_TGE				BIT27\r
\r
// AArch64 Exception Level\r
#define AARCH64_EL3       0xC\r
#define AARCH64_EL2       0x8\r
#define AARCH64_EL1       0x4\r
\r
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
\r
VOID\r
EFIAPI\r
ArmEnableSWPInstruction (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCbar (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadTpidrurw (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteTpidrurw (\r
  UINTN Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetTCR (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTCR (\r
  UINTN Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetMAIR (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetMAIR (\r
  UINTN Value\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableAlignmentCheck (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmEnableAlignmentCheck (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableAllExceptions (\r
  VOID\r
  );\r
\r
VOID\r
ArmWriteHcr (\r
  IN UINTN Hcr\r
  );\r
\r
UINTN\r
ArmReadCurrentEL (\r
  VOID\r
  );\r
\r
UINT64\r
PageAttributeToGcdAttribute (\r
  IN UINT64 PageAttributes\r
  );\r
\r
UINT64\r
GcdAttributeToPageAttribute (\r
  IN UINT64 GcdAttributes\r
  );\r
\r
#endif // __AARCH64_H__\r