projects / mirror_edk2.git / blame
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|---|---|---|
| 2ef2b01e A |
1 | /** @file\r |
| 2 | \r | |
| d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| bd6b9799 | 4 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r |
| 2ef2b01e | 5 | \r |
| d6ebcab7 | 6 | This program and the accompanying materials\r |
| 2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 5dea9bd6 | 16 | #ifndef __ARM_V7_H__\r |
| 17 | #define __ARM_V7_H__\r | |
| 2ef2b01e | 18 | \r |
| 11c20f4e | 19 | #include <Chipset/ArmV7Mmu.h>\r |
| 20 | \r | |
| 2ef2b01e A |
21 | // Domain Access Control Register\r |
| 22 | #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r | |
| 23 | #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r | |
| 24 | #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r | |
| 25 | #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r | |
| 26 | #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r | |
| 27 | \r | |
| 11c20f4e | 28 | // CPACR - Coprocessor Access Control Register definitions\r |
| 1bfda055 | 29 | #define CPACR_CP_DENIED(cp) 0x00\r |
| 30 | #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
| 31 | #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
| 32 | #define CPACR_ASEDIS (1 << 31)\r | |
| 33 | #define CPACR_D32DIS (1 << 30)\r | |
| 34 | #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r | |
| 35 | \r | |
| 11c20f4e | 36 | // NSACR - Non-Secure Access Control Register definitions\r |
| 1bfda055 | 37 | #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r |
| 38 | #define NSACR_NSD32DIS (1 << 14)\r | |
| 39 | #define NSACR_NSASEDIS (1 << 15)\r | |
| 40 | #define NSACR_PLE (1 << 16)\r | |
| 41 | #define NSACR_TL (1 << 17)\r | |
| 42 | #define NSACR_NS_SMP (1 << 18)\r | |
| 43 | #define NSACR_RFR (1 << 19)\r | |
| 44 | \r | |
| 11c20f4e | 45 | // SCR - Secure Configuration Register definitions\r |
| 1bfda055 | 46 | #define SCR_NS (1 << 0)\r |
| 47 | #define SCR_IRQ (1 << 1)\r | |
| 48 | #define SCR_FIQ (1 << 2)\r | |
| 49 | #define SCR_EA (1 << 3)\r | |
| 50 | #define SCR_FW (1 << 4)\r | |
| 51 | #define SCR_AW (1 << 5)\r | |
| 52 | \r | |
| bd6b9799 | 53 | // MIDR - Main ID Register definitions\r |
| 54 | #define ARM_CPU_TYPE_MASK 0xFFF\r | |
| 55 | #define ARM_CPU_TYPE_A15 0xC0F\r | |
| 56 | #define ARM_CPU_TYPE_A9 0xC09\r | |
| 57 | #define ARM_CPU_TYPE_A5 0xC05\r | |
| 1bfda055 | 58 | \r |
| 59 | VOID\r | |
| 60 | EFIAPI\r | |
| bd6b9799 | 61 | ArmEnableSWPInstruction (\r |
| 1bfda055 | 62 | VOID\r |
| 63 | );\r | |
| 64 | \r | |
| 1bfda055 | 65 | UINTN \r |
| 66 | EFIAPI\r | |
| 9e2b420e | 67 | ArmReadCbar (\r |
| 68 | VOID\r | |
| 69 | );\r | |
| 1bfda055 | 70 | \r |
| 0530bfe3 | 71 | UINTN\r |
| 72 | EFIAPI\r | |
| 9e2b420e | 73 | ArmReadTpidrurw (\r |
| 74 | VOID\r | |
| 75 | );\r | |
| 0530bfe3 | 76 | \r |
| 0530bfe3 | 77 | VOID\r |
| 78 | EFIAPI\r | |
| 9e2b420e | 79 | ArmWriteTpidrurw (\r |
| 80 | UINTN Value\r | |
| 81 | );\r | |
| 0530bfe3 | 82 | \r |
| bd6b9799 | 83 | UINTN\r |
| 84 | EFIAPI\r | |
| 85 | ArmReadIdPfr1 (\r | |
| 86 | VOID\r | |
| 87 | );\r | |
| 88 | \r | |
| 5dea9bd6 | 89 | #endif // __ARM_V7_H__\r |