[mirror_edk2.git] / ArmPkg / Include / Drivers / PL341Dmc.h

/** @file
*
*  Copyright (c) 2011, ARM Limited. All rights reserved.
*
*  This program and the accompanying materials
*  are licensed and made available under the terms and conditions of the BSD License
*  which accompanies this distribution.  The full text of the license may be found at
*  http://opensource.org/licenses/bsd-license.php
*
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/

#ifndef _PL341DMC_H_
#define _PL341DMC_H_


typedef struct  {
    UINTN	base;           // base address for the controller
    UINTN	phy_ctrl_base;	// DDR2 Phy control base
    UINTN	HasQos;        // has QoS registers
    UINTN	MaxChip;       // number of memory chips accessible
    BOOLEAN  IsUserCfg;
    UINT32  User0Cfg;
    UINT32  User2Cfg;
    UINT32	refresh_prd;
    UINT32	cas_latency;
    UINT32	write_latency;
    UINT32	t_mrd;
    UINT32	t_ras;
    UINT32	t_rc;
    UINT32	t_rcd;
    UINT32	t_rfc;
    UINT32	t_rp;
    UINT32	t_rrd;
    UINT32	t_wr;
    UINT32	t_wtr;
    UINT32	t_xp;
    UINT32	t_xsr;
    UINT32	t_esr;
    UINT32	MemoryCfg;
    UINT32	MemoryCfg2;
    UINT32	MemoryCfg3;
    UINT32	ChipCfg0;
    UINT32	ChipCfg1;
    UINT32	ChipCfg2;
    UINT32	ChipCfg3;
    UINT32	t_faw;
    UINT32	t_data_en;
    UINT32	t_wdata_en;
    UINT32  ModeReg;
    UINT32  ExtModeReg;
} PL341_DMC_CONFIG;

/* Memory config bit fields */
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)
#define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)
#define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)
#define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)
#define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1    (0x0 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2    (0x1 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3    (0x2 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4    (0x3 << 21)

#define DMC_MEMORY_CFG2_CLK_ASYNC    (0x0 << 0)
#define DMC_MEMORY_CFG2_CLK_SYNC    (0x1 << 0)
#define DMC_MEMORY_CFG2_DQM_INIT    (0x1 << 2)
#define DMC_MEMORY_CFG2_CKE_INIT    (0x1 << 3)
#define DMC_MEMORY_CFG2_BANK_BITS_2    (0x0 << 4)
#define DMC_MEMORY_CFG2_BANK_BITS_3    (0x3 << 4)
#define DMC_MEMORY_CFG2_MEM_WIDTH_16    (0x0 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_32    (0x1 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_64    (0x2 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED  (0x3 << 6)

//
// DMC Configuration Register Map
//
#define DMC_STATUS_REG              0x00
#define DMC_COMMAND_REG             0x04
#define DMC_DIRECT_CMD_REG          0x08
#define DMC_MEMORY_CONFIG_REG       0x0C
#define DMC_REFRESH_PRD_REG         0x10
#define DMC_CAS_LATENCY_REG         0x14
#define DMC_WRITE_LATENCY_REG       0x18
#define DMC_T_MRD_REG               0x1C
#define DMC_T_RAS_REG               0x20
#define DMC_T_RC_REG                0x24
#define DMC_T_RCD_REG               0x28
#define DMC_T_RFC_REG               0x2C
#define DMC_T_RP_REG                0x30
#define DMC_T_RRD_REG               0x34
#define DMC_T_WR_REG                0x38
#define DMC_T_WTR_REG               0x3C
#define DMC_T_XP_REG                0x40
#define DMC_T_XSR_REG               0x44
#define DMC_T_ESR_REG               0x48
#define DMC_MEMORY_CFG2_REG         0x4C
#define DMC_MEMORY_CFG3_REG         0x50
#define DMC_T_FAW_REG               0x54
#define DMC_T_RDATA_EN              0x5C	/* DFI read data enable register */
#define DMC_T_WRLAT_DIFF            0x60        /* DFI write data enable register */

// Returns the state of the memory controller:
#define DMC_STATUS_CONFIG       0x0
#define DMC_STATUS_READY        0x1
#define DMC_STATUS_PAUSED       0x2
#define DMC_STATUS_LOWPOWER     0x3

// Changes the state of the memory controller:
#define DMC_COMMAND_GO              0x0
#define DMC_COMMAND_SLEEP           0x1
#define DMC_COMMAND_WAKEUP          0x2
#define DMC_COMMAND_PAUSE           0x3
#define DMC_COMMAND_CONFIGURE       0x4
#define DMC_COMMAND_ACTIVEPAUSE     0x7

// Determines the command required
#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL      0x0
#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH       (0x1 << 18)
#define DMC_DIRECT_CMD_MEMCMD_MODEREG           (0x2 << 18)
#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG        (0x2 << 18)
#define DMC_DIRECT_CMD_MEMCMD_NOP               (0x3 << 18)
#define DMC_DIRECT_CMD_MEMCMD_DPD               (0x1 << 22)
#define DMC_DIRECT_CMD_BANKADDR(n)              ((n & 0x3) << 16)
#define DMC_DIRECT_CMD_CHIP_ADDR(n)             ((n & 0x3) << 20)


//
// AXI ID configuration register map
//
#define DMC_ID_0_CFG_REG            0x100
#define DMC_ID_1_CFG_REG            0x104
#define DMC_ID_2_CFG_REG            0x108
#define DMC_ID_3_CFG_REG            0x10C
#define DMC_ID_4_CFG_REG            0x110
#define DMC_ID_5_CFG_REG            0x114
#define DMC_ID_6_CFG_REG            0x118
#define DMC_ID_7_CFG_REG            0x11C
#define DMC_ID_8_CFG_REG            0x120
#define DMC_ID_9_CFG_REG            0x124
#define DMC_ID_10_CFG_REG           0x128
#define DMC_ID_11_CFG_REG           0x12C
#define DMC_ID_12_CFG_REG           0x130
#define DMC_ID_13_CFG_REG           0x134
#define DMC_ID_14_CFG_REG           0x138
#define DMC_ID_15_CFG_REG           0x13C

// Set the QoS
#define DMC_ID_CFG_QOS_DISABLE      0
#define DMC_ID_CFG_QOS_ENABLE       1
#define DMC_ID_CFG_QOS_MIN          2


//
// Chip configuration register map
//
#define DMC_CHIP_0_CFG_REG          0x200
#define DMC_CHIP_1_CFG_REG          0x204
#define DMC_CHIP_2_CFG_REG          0x208
#define DMC_CHIP_3_CFG_REG          0x20C

//
// User Defined Pins
//
#define DMC_USER_STATUS_REG         0x300
#define DMC_USER_0_CFG_REG          0x304
#define DMC_USER_1_CFG_REG          0x308
#define DMC_FEATURE_CRTL_REG        0x30C
#define DMC_USER_2_CFG_REG          0x310


//
// PHY Register Settings
//
#define PHY_PTM_DFI_CLK_RANGE					0xE00		// DDR2 PHY PTM register offset
#define PHY_PTM_IOTERM							0xE04
#define PHY_PTM_PLL_EN          				0xe0c
#define PHY_PTM_PLL_RANGE       				0xe18
#define PHY_PTM_FEEBACK_DIV     				0xe1c
#define PHY_PTM_RCLK_DIV        				0xe20
#define PHY_PTM_LOCK_STATUS     				0xe28
#define PHY_PTM_INIT_DONE	     				0xe34
#define PHY_PTM_ADDCOM_IOSTR_OFF				0xec8
#define PHY_PTM_SQU_TRAINING    				0xee8
#define PHY_PTM_SQU_STAT        				0xeec

// ==============================================================================
// PIPD 40G DDR2/DDR3 PHY Register definitions
//
// Offsets from APB Base Address
// ==============================================================================
#define PHY_BYTE0_OFFSET					0x000
#define PHY_BYTE1_OFFSET					0x200
#define PHY_BYTE2_OFFSET					0x400
#define PHY_BYTE3_OFFSET					0x600

#define PHY_BYTE0_COARSE_SQADJ_INIT			0x064	;// Coarse squelch adjust
#define PHY_BYTE1_COARSE_SQADJ_INIT			0x264	;// Coarse squelch adjust
#define PHY_BYTE2_COARSE_SQADJ_INIT			0x464	;// Coarse squelch adjust
#define PHY_BYTE3_COARSE_SQADJ_INIT			0x664	;// Coarse squelch adjust

#define PHY_BYTE0_IOSTR_OFFSET				0x004
#define PHY_BYTE1_IOSTR_OFFSET				0x204
#define PHY_BYTE2_IOSTR_OFFSET				0x404
#define PHY_BYTE3_IOSTR_OFFSET				0x604


;//--------------------------------------------------------------------------

// DFI Clock ranges:

#define PHY_PTM_DFI_CLK_RANGE_200MHz   		0x0
#define PHY_PTM_DFI_CLK_RANGE_201_267MHz	0x1
#define PHY_PTM_DFI_CLK_RANGE_268_333MHz	0x2
#define PHY_PTM_DFI_CLK_RANGE_334_400MHz	0x3
#define PHY_PTM_DFI_CLK_RANGE_401_533MHz	0x4
#define PHY_PTM_DFI_CLK_RANGE_534_667MHz	0x5
#define PHY_PTM_DFI_CLK_RANGE_668_800MHz	0x6


#define  PHY_PTM_DFI_CLK_RANGE_VAL			PHY_PTM_DFI_CLK_RANGE_334_400MHz

//--------------------------------------------------------------------------


// PLL Range

#define PHY_PTM_PLL_RANGE_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz
#define PHY_PTM_PLL_RANGE_400_800MHz		0x1	// b1 = frequency >= 400 MHz.
#define PHY_PTM_FEEBACK_DIV_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz
#define PHY_PTM_FEEBACK_DIV_400_800MHz		0x1	// b1 = frequency >= 400 MHz.
#define PHY_PTM_REFCLK_DIV_200_400MHz		0x0
#define PHY_PTM_REFCLK_DIV_400_800MHz		0x1


// PHY Reset in SCC

#define SCC_PHY_RST_REG_OFF	        		0xA0
#define SCC_REMAP_REG_OFF   	       		0x00
#define SCC_PHY_RST0_MASK					1		// Active LOW PHY0 reset
#define SCC_PHY_RST0_SHFT					0		// Active LOW PHY0 reset
#define SCC_PHY_RST1_MASK					0x100	// Active LOW PHY1 reset
#define SCC_PHY_RST1_SHFT					8		// Active LOW PHY1 reset

#define TC_UIOLHNC_MASK                         0x000003C0
#define TC_UIOLHNC_SHIFT                        0x6
#define TC_UIOLHPC_MASK                         0x0000003F
#define TC_UIOLHPC_SHIFT                        0x2
#define TC_UIOHOCT_MASK                         0x2
#define TC_UIOHOCT_SHIFT                        0x1
#define TC_UIOHSTOP_SHIFT                       0x0
#define TC_UIOLHXC_VALUE                        0x4

#define PHY_PTM_SQU_TRAINING_ENABLE				0x1
#define PHY_PTM_SQU_TRAINING_DISABLE				0x0


//--------------------------------------
// JEDEC DDR2 Device Register definitions and settings
//--------------------------------------
#define DDR_MODESET_SHFT						14
#define DDR_MODESET_MR							0x0		;// Mode register
#define DDR_MODESET_EMR							0x1		;// Extended Mode register
#define DDR_MODESET_EMR2						0x2
#define DDR_MODESET_EMR3						0x3

//
// Extended Mode Register settings
//
#define DDR_EMR_OCD_MASK                        0x0000380
#define DDR_EMR_OCD_SHIFT                       0x7
#define DDR_EMR_RTT_MASK                        0x00000044                  // DDR2 Device RTT (ODT) settings
#define DDR_EMR_RTT_SHIFT                       0x2
#define DDR_EMR_ODS_MASK                        0x00000002                  // DDR2 Output Drive Strength
#define DDR_EMR_ODS_SHIFT                       0x0001

// Termination Values:
#define DDR_EMR_RTT_50R                         0x00000044                  // DDR2 50 Ohm termination
#define DDR_EMR_RTT_75R                         0x00000004                  // DDR2 75 Ohm termination
#define DDR_EMR_RTT_150                         0x00000040                  // DDR2 150 Ohm termination

// Output Drive Strength Values:
#define DDR_EMR_ODS_FULL                        0x0                         // DDR2 Full Drive Strength
#define DDR_EMR_ODS_HALF                        0x1                         // DDR2 Half Drive Strength

// OCD values
#define DDR_EMR_OCD_DEFAULT                     0x7
#define DDR_EMR_OCD_NS                          0x0

#define DDR_EMR_ODS_VAL                         DDR_EMR_ODS_FULL

#define DDR_SDRAM_START_ADDR					0x10000000


// ----------------------------------------
// PHY IOTERM values
// ----------------------------------------
#define PHY_PTM_IOTERM_OFF					0x0
#define PHY_PTM_IOTERM_150R					0x1
#define PHY_PTM_IOTERM_75R					0x2
#define PHY_PTM_IOTERM_50R					0x3

#define PHY_BYTE_IOSTR_60OHM				0x0
#define PHY_BYTE_IOSTR_40OHM				0x1
#define PHY_BYTE_IOSTR_30OHM				0x2
#define PHY_BYTE_IOSTR_30AOHM				0x3

#define DDR2_MR_BURST_LENGTH_4     (2)
#define DDR2_MR_BURST_LENGTH_8     (3)
#define DDR2_MR_DLL_RESET          (1 << 8)
#define DDR2_MR_CAS_LATENCY_4      (4 << 4)
#define DDR2_MR_CAS_LATENCY_5      (5 << 4)
#define DDR2_MR_CAS_LATENCY_6      (6 << 4)
#define DDR2_MR_WR_CYCLES_2        (1 << 9)
#define DDR2_MR_WR_CYCLES_3        (2 << 9)
#define DDR2_MR_WR_CYCLES_4        (3 << 9)
#define DDR2_MR_WR_CYCLES_5        (4 << 9)
#define DDR2_MR_WR_CYCLES_6        (5 << 9)


VOID PL341DmcInit (
  IN PL341_DMC_CONFIG *config
  );

VOID PL341DmcPhyInit (
  IN UINTN   DmcPhyBase
  );

VOID PL341DmcTrainPHY (
  IN UINTN   DmcPhyBase
  );

#endif /* _PL341DMC_H_ */
Commit	Line	Data
1bfda055	1	/** @file
	2	*
	3	* Copyright (c) 2011, ARM Limited. All rights reserved.
	4	*
	5	* This program and the accompanying materials
	6	* are licensed and made available under the terms and conditions of the BSD License
	7	* which accompanies this distribution. The full text of the license may be found at
	8	* http://opensource.org/licenses/bsd-license.php
	9	*
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	*
	13	**/
	14
8be5d4d6	15	#ifndef _PL341DMC_H_
	16	#define _PL341DMC_H_
	17
	18
	19	typedef struct {
	20	UINTN base; // base address for the controller
	21	UINTN phy_ctrl_base; // DDR2 Phy control base
	22	UINTN HasQos; // has QoS registers
	23	UINTN MaxChip; // number of memory chips accessible
	24	BOOLEAN IsUserCfg;
	25	UINT32 User0Cfg;
	26	UINT32 User2Cfg;
	27	UINT32 refresh_prd;
	28	UINT32 cas_latency;
	29	UINT32 write_latency;
	30	UINT32 t_mrd;
	31	UINT32 t_ras;
	32	UINT32 t_rc;
	33	UINT32 t_rcd;
	34	UINT32 t_rfc;
	35	UINT32 t_rp;
	36	UINT32 t_rrd;
	37	UINT32 t_wr;
	38	UINT32 t_wtr;
	39	UINT32 t_xp;
	40	UINT32 t_xsr;
	41	UINT32 t_esr;
	42	UINT32 MemoryCfg;
	43	UINT32 MemoryCfg2;
	44	UINT32 MemoryCfg3;
	45	UINT32 ChipCfg0;
	46	UINT32 ChipCfg1;
	47	UINT32 ChipCfg2;
	48	UINT32 ChipCfg3;
	49	UINT32 t_faw;
	50	UINT32 t_data_en;
	51	UINT32 t_wdata_en;
	52	UINT32 ModeReg;
	53	UINT32 ExtModeReg;
	54	} PL341_DMC_CONFIG;
1bfda055	55
	56	/* Memory config bit fields */
	57	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
	58	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
	59	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
	60	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
	61	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
	62	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
	63	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
	64	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
	65	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
	66	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
	67	#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
	68	#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
	69	#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
	70	#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
2ac288f9	71	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
	72	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
	73	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
	74	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
1bfda055	75
2ac288f9	76	#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
	77	#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
	78	#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
	79	#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
	80	#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
	81	#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
	82	#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
	83	#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
	84	#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
	85	#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
1bfda055	86
8be5d4d6	87	//
	88	// DMC Configuration Register Map
	89	//
	90	#define DMC_STATUS_REG 0x00
	91	#define DMC_COMMAND_REG 0x04
	92	#define DMC_DIRECT_CMD_REG 0x08
	93	#define DMC_MEMORY_CONFIG_REG 0x0C
	94	#define DMC_REFRESH_PRD_REG 0x10
	95	#define DMC_CAS_LATENCY_REG 0x14
	96	#define DMC_WRITE_LATENCY_REG 0x18
	97	#define DMC_T_MRD_REG 0x1C
	98	#define DMC_T_RAS_REG 0x20
	99	#define DMC_T_RC_REG 0x24
	100	#define DMC_T_RCD_REG 0x28
	101	#define DMC_T_RFC_REG 0x2C
	102	#define DMC_T_RP_REG 0x30
	103	#define DMC_T_RRD_REG 0x34
	104	#define DMC_T_WR_REG 0x38
	105	#define DMC_T_WTR_REG 0x3C
	106	#define DMC_T_XP_REG 0x40
	107	#define DMC_T_XSR_REG 0x44
	108	#define DMC_T_ESR_REG 0x48
	109	#define DMC_MEMORY_CFG2_REG 0x4C
	110	#define DMC_MEMORY_CFG3_REG 0x50
	111	#define DMC_T_FAW_REG 0x54
	112	#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
	113	#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
	114
	115	// Returns the state of the memory controller:
	116	#define DMC_STATUS_CONFIG 0x0
	117	#define DMC_STATUS_READY 0x1
	118	#define DMC_STATUS_PAUSED 0x2
	119	#define DMC_STATUS_LOWPOWER 0x3
	120
	121	// Changes the state of the memory controller:
	122	#define DMC_COMMAND_GO 0x0
	123	#define DMC_COMMAND_SLEEP 0x1
	124	#define DMC_COMMAND_WAKEUP 0x2
	125	#define DMC_COMMAND_PAUSE 0x3
	126	#define DMC_COMMAND_CONFIGURE 0x4
	127	#define DMC_COMMAND_ACTIVEPAUSE 0x7
	128
	129	// Determines the command required
	130	#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
	131	#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
	132	#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
	133	#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
	134	#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
	135	#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
	136	#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
	137	#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
	138
	139
	140	//
	141	// AXI ID configuration register map
	142	//
	143	#define DMC_ID_0_CFG_REG 0x100
	144	#define DMC_ID_1_CFG_REG 0x104
	145	#define DMC_ID_2_CFG_REG 0x108
	146	#define DMC_ID_3_CFG_REG 0x10C
	147	#define DMC_ID_4_CFG_REG 0x110
	148	#define DMC_ID_5_CFG_REG 0x114
	149	#define DMC_ID_6_CFG_REG 0x118
	150	#define DMC_ID_7_CFG_REG 0x11C
151	#define DMC_ID_8_CFG_REG 0x120
152	#define DMC_ID_9_CFG_REG 0x124
153	#define DMC_ID_10_CFG_REG 0x128
154	#define DMC_ID_11_CFG_REG 0x12C
155	#define DMC_ID_12_CFG_REG 0x130
156	#define DMC_ID_13_CFG_REG 0x134
157	#define DMC_ID_14_CFG_REG 0x138
158	#define DMC_ID_15_CFG_REG 0x13C
159
160	// Set the QoS
161	#define DMC_ID_CFG_QOS_DISABLE 0
162	#define DMC_ID_CFG_QOS_ENABLE 1
163	#define DMC_ID_CFG_QOS_MIN 2
164
165
166	//
167	// Chip configuration register map
168	//
169	#define DMC_CHIP_0_CFG_REG 0x200
170	#define DMC_CHIP_1_CFG_REG 0x204
171	#define DMC_CHIP_2_CFG_REG 0x208
172	#define DMC_CHIP_3_CFG_REG 0x20C
173
174	//
175	// User Defined Pins
176	//
177	#define DMC_USER_STATUS_REG 0x300
178	#define DMC_USER_0_CFG_REG 0x304
179	#define DMC_USER_1_CFG_REG 0x308
180	#define DMC_FEATURE_CRTL_REG 0x30C
181	#define DMC_USER_2_CFG_REG 0x310
182
183
184	//
185	// PHY Register Settings
186	//
187	#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
188	#define PHY_PTM_IOTERM 0xE04
189	#define PHY_PTM_PLL_EN 0xe0c
190	#define PHY_PTM_PLL_RANGE 0xe18
191	#define PHY_PTM_FEEBACK_DIV 0xe1c
192	#define PHY_PTM_RCLK_DIV 0xe20
193	#define PHY_PTM_LOCK_STATUS 0xe28
194	#define PHY_PTM_INIT_DONE 0xe34
195	#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
196	#define PHY_PTM_SQU_TRAINING 0xee8
197	#define PHY_PTM_SQU_STAT 0xeec
198
199	// ==============================================================================
200	// PIPD 40G DDR2/DDR3 PHY Register definitions
201	//
202	// Offsets from APB Base Address
203	// ==============================================================================
204	#define PHY_BYTE0_OFFSET 0x000
205	#define PHY_BYTE1_OFFSET 0x200
206	#define PHY_BYTE2_OFFSET 0x400
207	#define PHY_BYTE3_OFFSET 0x600
208
209	#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
210	#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
211	#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
212	#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
213
214	#define PHY_BYTE0_IOSTR_OFFSET 0x004
215	#define PHY_BYTE1_IOSTR_OFFSET 0x204
216	#define PHY_BYTE2_IOSTR_OFFSET 0x404
217	#define PHY_BYTE3_IOSTR_OFFSET 0x604
218
219
220	;//--------------------------------------------------------------------------
221
222	// DFI Clock ranges:
223
224	#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
225	#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
226	#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
227	#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
228	#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
229	#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
230	#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
231
232
233
234	#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
235
236	//--------------------------------------------------------------------------
237
238
239	// PLL Range
240
241	#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
242	#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
243	#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
244	#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
245	#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
246	#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
247
248
249	// PHY Reset in SCC
250
251	#define SCC_PHY_RST_REG_OFF 0xA0
252	#define SCC_REMAP_REG_OFF 0x00
253	#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset
254	#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset
255	#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset
256	#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset
257
258	#define TC_UIOLHNC_MASK 0x000003C0
259	#define TC_UIOLHNC_SHIFT 0x6
260	#define TC_UIOLHPC_MASK 0x0000003F
261	#define TC_UIOLHPC_SHIFT 0x2
262	#define TC_UIOHOCT_MASK 0x2
263	#define TC_UIOHOCT_SHIFT 0x1
264	#define TC_UIOHSTOP_SHIFT 0x0
265	#define TC_UIOLHXC_VALUE 0x4
266
267	#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
268	#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
269
270
271	//--------------------------------------
272	// JEDEC DDR2 Device Register definitions and settings
273	//--------------------------------------
274	#define DDR_MODESET_SHFT 14
275	#define DDR_MODESET_MR 0x0 ;// Mode register
276	#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
277	#define DDR_MODESET_EMR2 0x2
278	#define DDR_MODESET_EMR3 0x3
279
280	//
281	// Extended Mode Register settings
282	//
283	#define DDR_EMR_OCD_MASK 0x0000380
284	#define DDR_EMR_OCD_SHIFT 0x7
285	#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
286	#define DDR_EMR_RTT_SHIFT 0x2
287	#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
288	#define DDR_EMR_ODS_SHIFT 0x0001
289
290	// Termination Values:
291	#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
292	#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
293	#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
294
295	// Output Drive Strength Values:
296	#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
297	#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
298
299	// OCD values
300	#define DDR_EMR_OCD_DEFAULT 0x7
301	#define DDR_EMR_OCD_NS 0x0
302
303	#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
304
305	#define DDR_SDRAM_START_ADDR 0x10000000
306
307
308	// ----------------------------------------
309	// PHY IOTERM values
310	// ----------------------------------------
311	#define PHY_PTM_IOTERM_OFF 0x0
312	#define PHY_PTM_IOTERM_150R 0x1
313	#define PHY_PTM_IOTERM_75R 0x2
314	#define PHY_PTM_IOTERM_50R 0x3
315
316	#define PHY_BYTE_IOSTR_60OHM 0x0
317	#define PHY_BYTE_IOSTR_40OHM 0x1
318	#define PHY_BYTE_IOSTR_30OHM 0x2
319	#define PHY_BYTE_IOSTR_30AOHM 0x3
320
321	#define DDR2_MR_BURST_LENGTH_4 (2)
322	#define DDR2_MR_BURST_LENGTH_8 (3)
323	#define DDR2_MR_DLL_RESET (1 << 8)
324	#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
325	#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
326	#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
327	#define DDR2_MR_WR_CYCLES_2 (1 << 9)
328	#define DDR2_MR_WR_CYCLES_3 (2 << 9)
329	#define DDR2_MR_WR_CYCLES_4 (3 << 9)
330	#define DDR2_MR_WR_CYCLES_5 (4 << 9)
331	#define DDR2_MR_WR_CYCLES_6 (5 << 9)
332
1bfda055	333
8be5d4d6	334	VOID PL341DmcInit (
	335	IN PL341_DMC_CONFIG *config
	336	);
1bfda055	337
8be5d4d6	338	VOID PL341DmcPhyInit (
	339	IN UINTN DmcPhyBase
	340	);
1bfda055	341
8be5d4d6	342	VOID PL341DmcTrainPHY (
	343	IN UINTN DmcPhyBase
	344	);
1bfda055	345
8be5d4d6	346	#endif /* _PL341DMC_H_ */