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9a9dd4e8 OM |
1 | /** @file\r |
2 | *\r | |
9e7621c0 | 3 | * Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r |
542bc11a | 4 | * Copyright (c) 2012-2017, ARM Limited. All rights reserved.\r |
9a9dd4e8 | 5 | *\r |
4059386c | 6 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9a9dd4e8 | 7 | *\r |
9e7621c0 RC |
8 | * @par Revision Reference:\r |
9 | * - SMC Calling Convention version 1.2\r | |
10 | * (https://developer.arm.com/documentation/den0028/c/?lang=en)\r | |
9a9dd4e8 OM |
11 | **/\r |
12 | \r | |
13 | #ifndef __ARM_STD_SMC_H__\r | |
14 | #define __ARM_STD_SMC_H__\r | |
15 | \r | |
16 | /*\r | |
17 | * SMC function IDs for Standard Service queries\r | |
18 | */\r | |
19 | \r | |
20 | #define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r | |
21 | #define ARM_SMC_ID_STD_UID 0x8400ff01\r | |
22 | /* 0x8400ff02 is reserved */\r | |
23 | #define ARM_SMC_ID_STD_REVISION 0x8400ff03\r | |
24 | \r | |
25 | /*\r | |
26 | * The 'Standard Service Call UID' is supposed to return the Standard\r | |
27 | * Service UUID. This is a 128-bit value.\r | |
28 | */\r | |
29 | #define ARM_SMC_STD_UUID0 0x108d905b\r | |
30 | #define ARM_SMC_STD_UUID1 0x47e8f863\r | |
31 | #define ARM_SMC_STD_UUID2 0xfbc02dae\r | |
32 | #define ARM_SMC_STD_UUID3 0xe2f64156\r | |
33 | \r | |
34 | /*\r | |
35 | * ARM Standard Service Calls revision numbers\r | |
36 | * The current revision is: 0.1\r | |
37 | */\r | |
38 | #define ARM_SMC_STD_REVISION_MAJOR 0x0\r | |
39 | #define ARM_SMC_STD_REVISION_MINOR 0x1\r | |
40 | \r | |
542bc11a SV |
41 | /*\r |
42 | * Management Mode (MM) calls cover a subset of the Standard Service Call range.\r | |
43 | * The list below is not exhaustive.\r | |
44 | */\r | |
45 | #define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040\r | |
46 | #define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040\r | |
47 | \r | |
48 | // Request service from secure standalone MM environment\r | |
49 | #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041\r | |
50 | #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041\r | |
51 | \r | |
52 | /* MM return error codes */\r | |
53 | #define ARM_SMC_MM_RET_SUCCESS 0\r | |
54 | #define ARM_SMC_MM_RET_NOT_SUPPORTED -1\r | |
55 | #define ARM_SMC_MM_RET_INVALID_PARAMS -2\r | |
56 | #define ARM_SMC_MM_RET_DENIED -3\r | |
57 | #define ARM_SMC_MM_RET_NO_MEMORY -4\r | |
58 | \r | |
9e7621c0 RC |
59 | // ARM Architecture Calls\r |
60 | #define SMCCC_VERSION 0x80000000\r | |
61 | #define SMCCC_ARCH_FEATURES 0x80000001\r | |
62 | #define SMCCC_ARCH_SOC_ID 0x80000002\r | |
63 | #define SMCCC_ARCH_WORKAROUND_1 0x80008000\r | |
64 | #define SMCCC_ARCH_WORKAROUND_2 0x80007FFF\r | |
65 | \r | |
66 | #define SMC_ARCH_CALL_SUCCESS 0\r | |
67 | #define SMC_ARCH_CALL_NOT_SUPPORTED -1\r | |
68 | #define SMC_ARCH_CALL_NOT_REQUIRED -2\r | |
69 | #define SMC_ARCH_CALL_INVALID_PARAMETER -3\r | |
70 | \r | |
9a9dd4e8 OM |
71 | /*\r |
72 | * Power State Coordination Interface (PSCI) calls cover a subset of the\r | |
73 | * Standard Service Call range.\r | |
74 | * The list below is not exhaustive.\r | |
75 | */\r | |
76 | #define ARM_SMC_ID_PSCI_VERSION 0x84000000\r | |
77 | #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64 0xc4000001\r | |
78 | #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32 0x84000001\r | |
79 | #define ARM_SMC_ID_PSCI_CPU_OFF 0x84000002\r | |
80 | #define ARM_SMC_ID_PSCI_CPU_ON_AARCH64 0xc4000003\r | |
81 | #define ARM_SMC_ID_PSCI_CPU_ON_AARCH32 0x84000003\r | |
82 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64 0xc4000004\r | |
83 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32 0x84000004\r | |
84 | #define ARM_SMC_ID_PSCI_MIGRATE_AARCH64 0xc4000005\r | |
85 | #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005\r | |
ae9bc057 AB |
86 | #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008\r |
87 | #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009\r | |
9a9dd4e8 OM |
88 | \r |
89 | /* The current PSCI version is: 0.2 */\r | |
90 | #define ARM_SMC_PSCI_VERSION_MAJOR 0\r | |
91 | #define ARM_SMC_PSCI_VERSION_MINOR 2\r | |
92 | #define ARM_SMC_PSCI_VERSION \\r | |
93 | ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)\r | |
94 | \r | |
95 | /* PSCI return error codes */\r | |
96 | #define ARM_SMC_PSCI_RET_SUCCESS 0\r | |
97 | #define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r | |
98 | #define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r | |
99 | #define ARM_SMC_PSCI_RET_DENIED -3\r | |
100 | #define ARM_SMC_PSCI_RET_ALREADY_ON -4\r | |
101 | #define ARM_SMC_PSCI_RET_ON_PENDING -5\r | |
102 | #define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r | |
103 | #define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r | |
104 | #define ARM_SMC_PSCI_RET_DISABLED -8\r | |
105 | \r | |
106 | #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \\r | |
107 | ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r | |
108 | \r | |
109 | #define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \\r | |
110 | ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r | |
111 | \r | |
112 | #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)\r | |
113 | #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)\r | |
114 | \r | |
115 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r | |
116 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r | |
117 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r | |
118 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r | |
119 | \r | |
120 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0\r | |
121 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1\r | |
122 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2\r | |
123 | \r | |
d65b78f1 SG |
124 | /*\r |
125 | * SMC function IDs for Trusted OS Service queries\r | |
126 | */\r | |
127 | #define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00\r | |
128 | #define ARM_SMC_ID_TOS_UID 0xbf00ff01\r | |
129 | /* 0xbf00ff02 is reserved */\r | |
130 | #define ARM_SMC_ID_TOS_REVISION 0xbf00ff03\r | |
131 | \r | |
9a9dd4e8 | 132 | #endif\r |