projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a9dd4e8 OM |
1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r | |
| 4 | *\r | |
| 5 | * This program and the accompanying materials\r | |
| 6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | * which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | * http://opensource.org/licenses/bsd-license.php\r | |
| 9 | *\r | |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | *\r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __ARM_STD_SMC_H__\r | |
| 16 | #define __ARM_STD_SMC_H__\r | |
| 17 | \r | |
| 18 | /*\r | |
| 19 | * SMC function IDs for Standard Service queries\r | |
| 20 | */\r | |
| 21 | \r | |
| 22 | #define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00\r | |
| 23 | #define ARM_SMC_ID_STD_UID 0x8400ff01\r | |
| 24 | /* 0x8400ff02 is reserved */\r | |
| 25 | #define ARM_SMC_ID_STD_REVISION 0x8400ff03\r | |
| 26 | \r | |
| 27 | /*\r | |
| 28 | * The 'Standard Service Call UID' is supposed to return the Standard\r | |
| 29 | * Service UUID. This is a 128-bit value.\r | |
| 30 | */\r | |
| 31 | #define ARM_SMC_STD_UUID0 0x108d905b\r | |
| 32 | #define ARM_SMC_STD_UUID1 0x47e8f863\r | |
| 33 | #define ARM_SMC_STD_UUID2 0xfbc02dae\r | |
| 34 | #define ARM_SMC_STD_UUID3 0xe2f64156\r | |
| 35 | \r | |
| 36 | /*\r | |
| 37 | * ARM Standard Service Calls revision numbers\r | |
| 38 | * The current revision is: 0.1\r | |
| 39 | */\r | |
| 40 | #define ARM_SMC_STD_REVISION_MAJOR 0x0\r | |
| 41 | #define ARM_SMC_STD_REVISION_MINOR 0x1\r | |
| 42 | \r | |
| 43 | /*\r | |
| 44 | * Power State Coordination Interface (PSCI) calls cover a subset of the\r | |
| 45 | * Standard Service Call range.\r | |
| 46 | * The list below is not exhaustive.\r | |
| 47 | */\r | |
| 48 | #define ARM_SMC_ID_PSCI_VERSION 0x84000000\r | |
| 49 | #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64 0xc4000001\r | |
| 50 | #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32 0x84000001\r | |
| 51 | #define ARM_SMC_ID_PSCI_CPU_OFF 0x84000002\r | |
| 52 | #define ARM_SMC_ID_PSCI_CPU_ON_AARCH64 0xc4000003\r | |
| 53 | #define ARM_SMC_ID_PSCI_CPU_ON_AARCH32 0x84000003\r | |
| 54 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64 0xc4000004\r | |
| 55 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32 0x84000004\r | |
| 56 | #define ARM_SMC_ID_PSCI_MIGRATE_AARCH64 0xc4000005\r | |
| 57 | #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005\r | |
| ae9bc057 AB |
58 | #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008\r |
| 59 | #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009\r | |
| 9a9dd4e8 OM |
60 | \r |
| 61 | /* The current PSCI version is: 0.2 */\r | |
| 62 | #define ARM_SMC_PSCI_VERSION_MAJOR 0\r | |
| 63 | #define ARM_SMC_PSCI_VERSION_MINOR 2\r | |
| 64 | #define ARM_SMC_PSCI_VERSION \\r | |
| 65 | ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)\r | |
| 66 | \r | |
| 67 | /* PSCI return error codes */\r | |
| 68 | #define ARM_SMC_PSCI_RET_SUCCESS 0\r | |
| 69 | #define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1\r | |
| 70 | #define ARM_SMC_PSCI_RET_INVALID_PARAMS -2\r | |
| 71 | #define ARM_SMC_PSCI_RET_DENIED -3\r | |
| 72 | #define ARM_SMC_PSCI_RET_ALREADY_ON -4\r | |
| 73 | #define ARM_SMC_PSCI_RET_ON_PENDING -5\r | |
| 74 | #define ARM_SMC_PSCI_RET_INTERN_FAIL -6\r | |
| 75 | #define ARM_SMC_PSCI_RET_NOT_PRESENT -7\r | |
| 76 | #define ARM_SMC_PSCI_RET_DISABLED -8\r | |
| 77 | \r | |
| 78 | #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \\r | |
| 79 | ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r | |
| 80 | \r | |
| 81 | #define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \\r | |
| 82 | ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))\r | |
| 83 | \r | |
| 84 | #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)\r | |
| 85 | #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)\r | |
| 86 | \r | |
| 87 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0\r | |
| 88 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1\r | |
| 89 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2\r | |
| 90 | #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3\r | |
| 91 | \r | |
| 92 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0\r | |
| 93 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1\r | |
| 94 | #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2\r | |
| 95 | \r | |
| 96 | #endif\r |