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2ef2b01e A |
1 | /** @file |
2 | ||
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
7fffeef9 | 4 | Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR> |
2ef2b01e | 5 | |
d6ebcab7 | 6 | This program and the accompanying materials |
2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License |
8 | which accompanies this distribution. The full text of the license may be found at | |
9 | http://opensource.org/licenses/bsd-license.php | |
10 | ||
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | ||
14 | **/ | |
15 | ||
16 | #ifndef __ARM_LIB__ | |
17 | #define __ARM_LIB__ | |
18 | ||
916666c0 | 19 | #include <Uefi/UefiBaseType.h> |
20 | ||
bd6b9799 | 21 | #ifdef ARM_CPU_ARMv6 |
22 | #include <Chipset/ARM1176JZ-S.h> | |
23 | #else | |
24 | #include <Chipset/ArmV7.h> | |
25 | #endif | |
26 | ||
2ef2b01e A |
27 | typedef enum { |
28 | ARM_CACHE_TYPE_WRITE_BACK, | |
29 | ARM_CACHE_TYPE_UNKNOWN | |
30 | } ARM_CACHE_TYPE; | |
31 | ||
32 | typedef enum { | |
33 | ARM_CACHE_ARCHITECTURE_UNIFIED, | |
34 | ARM_CACHE_ARCHITECTURE_SEPARATE, | |
35 | ARM_CACHE_ARCHITECTURE_UNKNOWN | |
36 | } ARM_CACHE_ARCHITECTURE; | |
37 | ||
38 | typedef struct { | |
39 | ARM_CACHE_TYPE Type; | |
40 | ARM_CACHE_ARCHITECTURE Architecture; | |
41 | BOOLEAN DataCachePresent; | |
42 | UINTN DataCacheSize; | |
43 | UINTN DataCacheAssociativity; | |
44 | UINTN DataCacheLineLength; | |
45 | BOOLEAN InstructionCachePresent; | |
46 | UINTN InstructionCacheSize; | |
47 | UINTN InstructionCacheAssociativity; | |
48 | UINTN InstructionCacheLineLength; | |
49 | } ARM_CACHE_INFO; | |
50 | ||
7fffeef9 | 51 | /** |
52 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. | |
53 | * | |
54 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only | |
55 | * be used in Secure World to distinguished Secure to Non-Secure memory. | |
56 | */ | |
2ef2b01e | 57 | typedef enum { |
1e6a5cfc | 58 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, |
7fffeef9 | 59 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, |
1e6a5cfc | 60 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, |
7fffeef9 | 61 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, |
1e6a5cfc | 62 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, |
7fffeef9 | 63 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH, |
1e6a5cfc | 64 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, |
7fffeef9 | 65 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE |
2ef2b01e A |
66 | } ARM_MEMORY_REGION_ATTRIBUTES; |
67 | ||
1e6a5cfc | 68 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) |
69 | ||
2ef2b01e | 70 | typedef struct { |
916666c0 | 71 | EFI_PHYSICAL_ADDRESS PhysicalBase; |
72 | EFI_VIRTUAL_ADDRESS VirtualBase; | |
3b73c91b | 73 | UINTN Length; |
2ef2b01e A |
74 | ARM_MEMORY_REGION_ATTRIBUTES Attributes; |
75 | } ARM_MEMORY_REGION_DESCRIPTOR; | |
76 | ||
77 | typedef VOID (*CACHE_OPERATION)(VOID); | |
78 | typedef VOID (*LINE_OPERATION)(UINTN); | |
79 | ||
1e404316 | 80 | // |
81 | // ARM Processor Mode | |
82 | // | |
2ef2b01e A |
83 | typedef enum { |
84 | ARM_PROCESSOR_MODE_USER = 0x10, | |
85 | ARM_PROCESSOR_MODE_FIQ = 0x11, | |
86 | ARM_PROCESSOR_MODE_IRQ = 0x12, | |
87 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, | |
88 | ARM_PROCESSOR_MODE_ABORT = 0x17, | |
0e9674e5 | 89 | ARM_PROCESSOR_MODE_HYP = 0x1A, |
2ef2b01e A |
90 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, |
91 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F, | |
92 | ARM_PROCESSOR_MODE_MASK = 0x1F | |
93 | } ARM_PROCESSOR_MODE; | |
94 | ||
1e404316 | 95 | // |
96 | // ARM Cpu IDs | |
97 | // | |
2575b726 | 98 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24) |
99 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24) | |
100 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24) | |
101 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24) | |
102 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24) | |
103 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24) | |
1e404316 | 104 | |
105 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) | |
106 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) | |
107 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4) | |
108 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4) | |
109 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4) | |
110 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4) | |
9133aa80 | 111 | |
112 | // | |
113 | // ARM MP Core IDs | |
114 | // | |
0787bc61 | 115 | #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) |
9133aa80 | 116 | #define ARM_CORE_MASK 0xFF |
117 | #define ARM_CLUSTER_MASK (0xFF << 8) | |
118 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) | |
119 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) | |
0787bc61 | 120 | // Get the position of the core for the Stack Offset (4 Core per Cluster) |
121 | // Position = (ClusterId * 4) + CoreId | |
9133aa80 | 122 | #define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK)) |
123 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) | |
0787bc61 | 124 | |
2ef2b01e A |
125 | ARM_CACHE_TYPE |
126 | EFIAPI | |
127 | ArmCacheType ( | |
128 | VOID | |
129 | ); | |
130 | ||
131 | ARM_CACHE_ARCHITECTURE | |
132 | EFIAPI | |
133 | ArmCacheArchitecture ( | |
134 | VOID | |
135 | ); | |
136 | ||
137 | VOID | |
138 | EFIAPI | |
139 | ArmCacheInformation ( | |
140 | OUT ARM_CACHE_INFO *CacheInfo | |
141 | ); | |
142 | ||
143 | BOOLEAN | |
144 | EFIAPI | |
145 | ArmDataCachePresent ( | |
146 | VOID | |
147 | ); | |
148 | ||
149 | UINTN | |
150 | EFIAPI | |
151 | ArmDataCacheSize ( | |
152 | VOID | |
153 | ); | |
154 | ||
155 | UINTN | |
156 | EFIAPI | |
157 | ArmDataCacheAssociativity ( | |
158 | VOID | |
159 | ); | |
160 | ||
161 | UINTN | |
162 | EFIAPI | |
163 | ArmDataCacheLineLength ( | |
164 | VOID | |
165 | ); | |
166 | ||
167 | BOOLEAN | |
168 | EFIAPI | |
169 | ArmInstructionCachePresent ( | |
170 | VOID | |
171 | ); | |
172 | ||
173 | UINTN | |
174 | EFIAPI | |
175 | ArmInstructionCacheSize ( | |
176 | VOID | |
177 | ); | |
178 | ||
179 | UINTN | |
180 | EFIAPI | |
181 | ArmInstructionCacheAssociativity ( | |
182 | VOID | |
183 | ); | |
184 | ||
185 | UINTN | |
186 | EFIAPI | |
187 | ArmInstructionCacheLineLength ( | |
188 | VOID | |
189 | ); | |
190 | ||
191 | UINT32 | |
192 | EFIAPI | |
193 | Cp15IdCode ( | |
194 | VOID | |
195 | ); | |
196 | ||
197 | UINT32 | |
198 | EFIAPI | |
199 | Cp15CacheInfo ( | |
200 | VOID | |
201 | ); | |
202 | ||
1bfda055 | 203 | BOOLEAN |
204 | EFIAPI | |
da9675a2 | 205 | ArmIsMpCore ( |
1bfda055 | 206 | VOID |
207 | ); | |
208 | ||
2ef2b01e A |
209 | VOID |
210 | EFIAPI | |
211 | ArmInvalidateDataCache ( | |
212 | VOID | |
213 | ); | |
214 | ||
f45ce9d9 | 215 | |
2ef2b01e A |
216 | VOID |
217 | EFIAPI | |
218 | ArmCleanInvalidateDataCache ( | |
219 | VOID | |
220 | ); | |
221 | ||
222 | VOID | |
223 | EFIAPI | |
224 | ArmCleanDataCache ( | |
225 | VOID | |
226 | ); | |
227 | ||
d60f6af4 | 228 | VOID |
229 | EFIAPI | |
230 | ArmCleanDataCacheToPoU ( | |
231 | VOID | |
232 | ); | |
233 | ||
2ef2b01e A |
234 | VOID |
235 | EFIAPI | |
236 | ArmInvalidateInstructionCache ( | |
237 | VOID | |
238 | ); | |
239 | ||
240 | VOID | |
241 | EFIAPI | |
242 | ArmInvalidateDataCacheEntryByMVA ( | |
243 | IN UINTN Address | |
244 | ); | |
245 | ||
246 | VOID | |
247 | EFIAPI | |
248 | ArmCleanDataCacheEntryByMVA ( | |
249 | IN UINTN Address | |
250 | ); | |
251 | ||
252 | VOID | |
253 | EFIAPI | |
254 | ArmCleanInvalidateDataCacheEntryByMVA ( | |
255 | IN UINTN Address | |
256 | ); | |
257 | ||
258 | VOID | |
259 | EFIAPI | |
260 | ArmEnableDataCache ( | |
261 | VOID | |
262 | ); | |
263 | ||
264 | VOID | |
265 | EFIAPI | |
266 | ArmDisableDataCache ( | |
267 | VOID | |
268 | ); | |
269 | ||
270 | VOID | |
271 | EFIAPI | |
272 | ArmEnableInstructionCache ( | |
273 | VOID | |
274 | ); | |
275 | ||
276 | VOID | |
277 | EFIAPI | |
278 | ArmDisableInstructionCache ( | |
279 | VOID | |
280 | ); | |
281 | ||
282 | VOID | |
283 | EFIAPI | |
284 | ArmEnableMmu ( | |
285 | VOID | |
286 | ); | |
287 | ||
288 | VOID | |
289 | EFIAPI | |
290 | ArmDisableMmu ( | |
291 | VOID | |
292 | ); | |
293 | ||
1bfda055 | 294 | VOID |
295 | EFIAPI | |
296 | ArmDisableCachesAndMmu ( | |
297 | VOID | |
298 | ); | |
299 | ||
bd6b9799 | 300 | VOID |
301 | EFIAPI | |
302 | ArmInvalidateInstructionAndDataTlb ( | |
303 | VOID | |
304 | ); | |
305 | ||
2ef2b01e A |
306 | VOID |
307 | EFIAPI | |
308 | ArmEnableInterrupts ( | |
309 | VOID | |
310 | ); | |
311 | ||
312 | UINTN | |
313 | EFIAPI | |
314 | ArmDisableInterrupts ( | |
315 | VOID | |
316 | ); | |
317 | ||
318 | BOOLEAN | |
319 | EFIAPI | |
320 | ArmGetInterruptState ( | |
321 | VOID | |
322 | ); | |
1bfda055 | 323 | |
0416278c | 324 | VOID |
325 | EFIAPI | |
326 | ArmEnableFiq ( | |
327 | VOID | |
328 | ); | |
329 | ||
330 | UINTN | |
331 | EFIAPI | |
332 | ArmDisableFiq ( | |
333 | VOID | |
334 | ); | |
335 | ||
336 | BOOLEAN | |
337 | EFIAPI | |
338 | ArmGetFiqState ( | |
339 | VOID | |
340 | ); | |
2ef2b01e A |
341 | |
342 | VOID | |
343 | EFIAPI | |
344 | ArmInvalidateTlb ( | |
345 | VOID | |
346 | ); | |
347 | ||
6f72e28d | 348 | VOID |
349 | EFIAPI | |
350 | ArmUpdateTranslationTableEntry ( | |
bb02cb80 | 351 | IN VOID *TranslationTableEntry, |
352 | IN VOID *Mva | |
6f72e28d | 353 | ); |
354 | ||
2ef2b01e A |
355 | VOID |
356 | EFIAPI | |
357 | ArmSetDomainAccessControl ( | |
358 | IN UINT32 Domain | |
359 | ); | |
360 | ||
361 | VOID | |
362 | EFIAPI | |
1bfda055 | 363 | ArmSetTTBR0 ( |
2ef2b01e A |
364 | IN VOID *TranslationTableBase |
365 | ); | |
366 | ||
f45ce9d9 A |
367 | VOID * |
368 | EFIAPI | |
1bfda055 | 369 | ArmGetTTBR0BaseAddress ( |
f659880b | 370 | VOID |
f45ce9d9 A |
371 | ); |
372 | ||
2ef2b01e A |
373 | VOID |
374 | EFIAPI | |
375 | ArmConfigureMmu ( | |
376 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
377 | OUT VOID **TranslationTableBase OPTIONAL, | |
378 | OUT UINTN *TranslationTableSize OPTIONAL | |
379 | ); | |
380 | ||
f45ce9d9 A |
381 | BOOLEAN |
382 | EFIAPI | |
383 | ArmMmuEnabled ( | |
384 | VOID | |
385 | ); | |
386 | ||
2ef2b01e A |
387 | VOID |
388 | EFIAPI | |
389 | ArmSwitchProcessorMode ( | |
390 | IN ARM_PROCESSOR_MODE Mode | |
391 | ); | |
392 | ||
393 | ARM_PROCESSOR_MODE | |
394 | EFIAPI | |
395 | ArmProcessorMode ( | |
396 | VOID | |
397 | ); | |
398 | ||
399 | VOID | |
400 | EFIAPI | |
401 | ArmEnableBranchPrediction ( | |
402 | VOID | |
403 | ); | |
404 | ||
405 | VOID | |
406 | EFIAPI | |
407 | ArmDisableBranchPrediction ( | |
408 | VOID | |
409 | ); | |
f0fef790 | 410 | |
411 | VOID | |
412 | EFIAPI | |
413 | ArmSetLowVectors ( | |
414 | VOID | |
415 | ); | |
416 | ||
417 | VOID | |
418 | EFIAPI | |
419 | ArmSetHighVectors ( | |
420 | VOID | |
421 | ); | |
422 | ||
026c3d34 | 423 | VOID |
424 | EFIAPI | |
425 | ArmDataMemoryBarrier ( | |
426 | VOID | |
427 | ); | |
428 | ||
429 | VOID | |
430 | EFIAPI | |
431 | ArmDataSyncronizationBarrier ( | |
432 | VOID | |
433 | ); | |
434 | ||
435 | VOID | |
436 | EFIAPI | |
437 | ArmInstructionSynchronizationBarrier ( | |
438 | VOID | |
439 | ); | |
bd6b9799 | 440 | |
441 | VOID | |
442 | EFIAPI | |
443 | ArmWriteVBar ( | |
444 | IN UINT32 VectorBase | |
445 | ); | |
446 | ||
447 | UINT32 | |
448 | EFIAPI | |
449 | ArmReadVBar ( | |
450 | VOID | |
451 | ); | |
452 | ||
453 | VOID | |
454 | EFIAPI | |
455 | ArmWriteAuxCr ( | |
456 | IN UINT32 Bit | |
457 | ); | |
458 | ||
459 | UINT32 | |
460 | EFIAPI | |
461 | ArmReadAuxCr ( | |
462 | VOID | |
463 | ); | |
464 | ||
465 | VOID | |
466 | EFIAPI | |
467 | ArmSetAuxCrBit ( | |
468 | IN UINT32 Bits | |
469 | ); | |
470 | ||
836c3500 | 471 | VOID |
472 | EFIAPI | |
473 | ArmUnsetAuxCrBit ( | |
474 | IN UINT32 Bits | |
475 | ); | |
476 | ||
bd6b9799 | 477 | VOID |
478 | EFIAPI | |
b1d41be7 | 479 | ArmCallSEV ( |
480 | VOID | |
481 | ); | |
482 | ||
483 | VOID | |
484 | EFIAPI | |
485 | ArmCallWFE ( | |
486 | VOID | |
487 | ); | |
488 | ||
836c3500 | 489 | VOID |
490 | EFIAPI | |
bd6b9799 | 491 | ArmCallWFI ( |
492 | VOID | |
493 | ); | |
494 | ||
495 | UINTN | |
496 | EFIAPI | |
497 | ArmReadMpidr ( | |
498 | VOID | |
499 | ); | |
500 | ||
836c3500 | 501 | UINT32 |
502 | EFIAPI | |
503 | ArmReadCpacr ( | |
504 | VOID | |
505 | ); | |
506 | ||
bd6b9799 | 507 | VOID |
508 | EFIAPI | |
836c3500 | 509 | ArmWriteCpacr ( |
bd6b9799 | 510 | IN UINT32 Access |
511 | ); | |
512 | ||
513 | VOID | |
514 | EFIAPI | |
515 | ArmEnableVFP ( | |
516 | VOID | |
517 | ); | |
518 | ||
836c3500 | 519 | UINT32 |
520 | EFIAPI | |
521 | ArmReadNsacr ( | |
522 | VOID | |
523 | ); | |
524 | ||
bd6b9799 | 525 | VOID |
526 | EFIAPI | |
527 | ArmWriteNsacr ( | |
528 | IN UINT32 SetWayFormat | |
529 | ); | |
530 | ||
836c3500 | 531 | UINT32 |
532 | EFIAPI | |
533 | ArmReadScr ( | |
534 | VOID | |
535 | ); | |
536 | ||
bd6b9799 | 537 | VOID |
538 | EFIAPI | |
539 | ArmWriteScr ( | |
540 | IN UINT32 SetWayFormat | |
541 | ); | |
542 | ||
836c3500 | 543 | UINT32 |
544 | EFIAPI | |
545 | ArmReadMVBar ( | |
546 | VOID | |
547 | ); | |
548 | ||
bd6b9799 | 549 | VOID |
550 | EFIAPI | |
836c3500 | 551 | ArmWriteMVBar ( |
bd6b9799 | 552 | IN UINT32 VectorMonitorBase |
553 | ); | |
bb02cb80 | 554 | |
836c3500 | 555 | UINT32 |
556 | EFIAPI | |
557 | ArmReadSctlr ( | |
558 | VOID | |
559 | ); | |
560 | ||
2ef2b01e | 561 | #endif // __ARM_LIB__ |