ArmPkg/ArmLib: don't invalidate entire I-cache on range operation

[mirror_edk2.git] / ArmPkg / Library / ArmCacheMaintenanceLib / ArmCacheMaintenanceLib.c

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#include <Base.h>\r
#include <Library/ArmLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
STATIC\r
VOID\r
CacheRangeOperation (\r
  IN  VOID            *Start,\r
  IN  UINTN           Length,\r
  IN  LINE_OPERATION  LineOperation,\r
  IN  UINTN           LineLength\r
  )\r
{\r
  UINTN ArmCacheLineAlignmentMask  = LineLength - 1;\r
\r
  // Align address (rounding down)\r
  UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r
  UINTN EndAddress     = (UINTN)Start + Length;\r
\r
  // Perform the line operation on an address in each cache line\r
  while (AlignedAddress < EndAddress) {\r
    LineOperation(AlignedAddress);\r
    AlignedAddress += LineLength;\r
  }\r
  ArmDataSynchronizationBarrier ();\r
}\r
\r
VOID\r
EFIAPI\r
InvalidateInstructionCache (\r
  VOID\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r
VOID\r
EFIAPI\r
InvalidateDataCache (\r
  VOID\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,\r
    ArmDataCacheLineLength ());\r
  CacheRangeOperation (Address, Length,\r
    ArmInvalidateInstructionCacheEntryToPoUByMVA,\r
    ArmInstructionCacheLineLength ());\r
\r
  ArmInstructionSynchronizationBarrier ();\r
\r
  return Address;\r
}\r
\r
VOID\r
EFIAPI\r
WriteBackInvalidateDataCache (\r
  VOID\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,\r
    ArmDataCacheLineLength ());\r
  return Address;\r
}\r
\r
VOID\r
EFIAPI\r
WriteBackDataCache (\r
  VOID\r
  )\r
{\r
  ASSERT (FALSE);\r
}\r
\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,\r
    ArmDataCacheLineLength ());\r
  return Address;\r
}\r
\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
  IN      VOID                      *Address,\r
  IN      UINTN                     Length\r
  )\r
{\r
  CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,\r
    ArmDataCacheLineLength ());\r
  return Address;\r
}\r