ArmPkg: Apply uncrustify changes

[mirror_edk2.git] / ArmPkg / Library / ArmDisassemblerLib / ArmDisassembler.c

/** @file\r
  Default exception handler\r
\r
  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Base.h>\r
#include <Library/BaseLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/ArmDisassemblerLib.h>\r
\r
CHAR8  *gCondition[] = {\r
  "EQ",\r
  "NE",\r
  "CS",\r
  "CC",\r
  "MI",\r
  "PL",\r
  "VS",\r
  "VC",\r
  "HI",\r
  "LS",\r
  "GE",\r
  "LT",\r
  "GT",\r
  "LE",\r
  "",\r
  "2"\r
};\r
\r
#define COND(_a)  gCondition[((_a) >> 28)]\r
\r
CHAR8  *gReg[] = {\r
  "r0",\r
  "r1",\r
  "r2",\r
  "r3",\r
  "r4",\r
  "r5",\r
  "r6",\r
  "r7",\r
  "r8",\r
  "r9",\r
  "r10",\r
  "r11",\r
  "r12",\r
  "sp",\r
  "lr",\r
  "pc"\r
};\r
\r
CHAR8  *gLdmAdr[] = {\r
  "DA",\r
  "IA",\r
  "DB",\r
  "IB"\r
};\r
\r
CHAR8  *gLdmStack[] = {\r
  "FA",\r
  "FD",\r
  "EA",\r
  "ED"\r
};\r
\r
#define LDM_EXT(_reg, _off)  ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])\r
\r
#define SIGN(_U)       ((_U) ? "" : "-")\r
#define WRITE(_Write)  ((_Write) ? "!" : "")\r
#define BYTE(_B)       ((_B) ? "B":"")\r
#define USER(_B)       ((_B) ? "^" : "")\r
\r
CHAR8  mMregListStr[4*15 + 1];\r
\r
CHAR8 *\r
MRegList (\r
  UINT32  OpCode\r
  )\r
{\r
  UINTN    Index, Start, End;\r
  BOOLEAN  First;\r
\r
  mMregListStr[0] = '\0';\r
  AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");\r
  for (Index = 0, First = TRUE; Index <= 15; Index++) {\r
    if ((OpCode & (1 << Index)) != 0) {\r
      Start = End = Index;\r
      for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {\r
        End = Index;\r
      }\r
\r
      if (!First) {\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, ",");\r
      } else {\r
        First = FALSE;\r
      }\r
\r
      if (Start == End) {\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, ", ");\r
      } else {\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, "-");\r
        AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[End]);\r
      }\r
    }\r
  }\r
\r
  if (First) {\r
    AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");\r
  }\r
\r
  AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");\r
\r
  // BugBug: Make caller pass in buffer it is cleaner\r
  return mMregListStr;\r
}\r
\r
CHAR8 *\r
FieldMask (\r
  IN  UINT32  Mask\r
  )\r
{\r
  return "";\r
}\r
\r
UINT32\r
RotateRight (\r
  IN UINT32  Op,\r
  IN UINT32  Shift\r
  )\r
{\r
  return (Op >> Shift) | (Op << (32 - Shift));\r
}\r
\r
/**\r
  Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
  point to next instruction.\r
\r
  We cheat and only decode instructions that access\r
  memory. If the instruction is not found we dump the instruction in hex.\r
\r
  @param  OpCodePtr   Pointer to pointer of ARM instruction to disassemble.\r
  @param  Buf         Buffer to sprintf disassembly into.\r
  @param  Size        Size of Buf in bytes.\r
  @param  Extended    TRUE dump hex for instruction too.\r
\r
**/\r
VOID\r
DisassembleArmInstruction (\r
  IN  UINT32   **OpCodePtr,\r
  OUT CHAR8    *Buf,\r
  OUT UINTN    Size,\r
  IN  BOOLEAN  Extended\r
  )\r
{\r
  UINT32   OpCode;\r
  CHAR8    *Type;\r
  CHAR8    *Root;\r
  BOOLEAN  Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;\r
  UINT32   Rn, Rd, Rm;\r
  UINT32   IMod, Offset8, Offset12;\r
  UINT32   Index;\r
  UINT32   ShiftImm, Shift;\r
\r
  OpCode = **OpCodePtr;\r
\r
  Imm       = (OpCode & BIT25) == BIT25; // I\r
  Pre       = (OpCode & BIT24) == BIT24; // P\r
  Up        = (OpCode & BIT23) == BIT23; // U\r
  WriteBack = (OpCode & BIT22) == BIT22; // B, also called S\r
  Write     = (OpCode & BIT21) == BIT21; // W\r
  Load      = (OpCode & BIT20) == BIT20; // L\r
  Sign      = (OpCode & BIT6) == BIT6;   // S\r
  Half      = (OpCode & BIT5) == BIT5;   // H\r
  Rn        = (OpCode >> 16) & 0xf;\r
  Rd        = (OpCode >> 12) & 0xf;\r
  Rm        = (OpCode & 0xf);\r
\r
  if (Extended) {\r
    Index = AsciiSPrint (Buf, Size, "0x%08x   ", OpCode);\r
    Buf  += Index;\r
    Size -= Index;\r
  }\r
\r
  // LDREX, STREX\r
  if ((OpCode  & 0x0fe000f0) == 0x01800090) {\r
    if (Load) {\r
      // A4.1.27  LDREX{<cond>} <Rd>, [<Rn>]\r
      AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);\r
    } else {\r
      // A4.1.103  STREX{<cond>} <Rd>, <Rm>, [<Rn>]\r
      AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);\r
    }\r
\r
    return;\r
  }\r
\r
  // LDM/STM\r
  if ((OpCode  & 0x0e000000) == 0x08000000) {\r
    if (Load) {\r
      // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
      // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^\r
      // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^\r
      AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
    } else {\r
      // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
      // A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^\r
      AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));\r
    }\r
\r
    return;\r
  }\r
\r
  // LDR/STR Address Mode 2\r
  if (((OpCode  & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {\r
    Offset12 = OpCode & 0xfff;\r
    if ((OpCode & 0xfd70f000) == 0xf550f000) {\r
      Index = AsciiSPrint (Buf, Size, "PLD");\r
    } else {\r
      Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);\r
    }\r
\r
    if (Pre) {\r
      if (!Imm) {\r
        // A5.2.2 [<Rn>, #+/-<offset_12>]\r
        // A5.2.5 [<Rn>, #+/-<offset_12>]\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));\r
      } else if ((OpCode & 0x03000ff0) == 0x03000000) {\r
        // A5.2.3 [<Rn>, +/-<Rm>]\r
        // A5.2.6 [<Rn>, +/-<Rm>]!\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));\r
      } else {\r
        // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]\r
        // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!\r
        ShiftImm = (OpCode >> 7) & 0x1f;\r
        Shift    = (OpCode >> 5) & 0x3;\r
        if (Shift == 0x0) {\r
          Type = "LSL";\r
        } else if (Shift == 0x1) {\r
          Type = "LSR";\r
          if (ShiftImm == 0) {\r
            ShiftImm = 32;\r
          }\r
        } else if (Shift == 0x2) {\r
          Type = "ASR";\r
        } else if (ShiftImm == 0) {\r
          AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
          return;\r
        } else {\r
          Type = "ROR";\r
        }\r
\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));\r
      }\r
    } else {\r
      // !Pre\r
      if (!Imm) {\r
        // A5.2.8  [<Rn>], #+/-<offset_12>\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);\r
      } else if ((OpCode & 0x03000ff0) == 0x03000000) {\r
        // A5.2.9  [<Rn>], +/-<Rm>\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
      } else {\r
        // A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>\r
        ShiftImm = (OpCode >> 7) & 0x1f;\r
        Shift    = (OpCode >> 5) & 0x3;\r
\r
        if (Shift == 0x0) {\r
          Type = "LSL";\r
        } else if (Shift == 0x1) {\r
          Type = "LSR";\r
          if (ShiftImm == 0) {\r
            ShiftImm = 32;\r
          }\r
        } else if (Shift == 0x2) {\r
          Type = "ASR";\r
        } else if (ShiftImm == 0) {\r
          AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);\r
          // FIx me\r
          return;\r
        } else {\r
          Type = "ROR";\r
        }\r
\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);\r
      }\r
    }\r
\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0e000000) == 0x00000000) {\r
    // LDR/STR address mode 3\r
    // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>\r
    if (Load) {\r
      if (!Sign) {\r
        Root = "LDR%aH %a, ";\r
      } else if (!Half) {\r
        Root = "LDR%aSB %a, ";\r
      } else {\r
        Root = "LDR%aSH %a, ";\r
      }\r
    } else {\r
      if (!Sign) {\r
        Root = "STR%aH %a ";\r
      } else if (!Half) {\r
        Root = "LDR%aD %a ";\r
      } else {\r
        Root = "STR%aD %a ";\r
      }\r
    }\r
\r
    Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);\r
\r
    Sign    = (OpCode & BIT6) == BIT6;\r
    Half    = (OpCode & BIT5) == BIT5;\r
    Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;\r
    if (Pre & !Write) {\r
      // Immediate offset/index\r
      if (WriteBack) {\r
        // A5.3.2  [<Rn>, #+/-<offset_8>]\r
        // A5.3.4  [<Rn>, #+/-<offset_8>]!\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));\r
      } else {\r
        // A5.3.3  [<Rn>, +/-<Rm>]\r
        // A5.3.5  [<Rn>, +/-<Rm>]!\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));\r
      }\r
    } else {\r
      // Register offset/index\r
      if (WriteBack) {\r
        // A5.3.6 [<Rn>], #+/-<offset_8>\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);\r
      } else {\r
        // A5.3.7 [<Rn>], +/-<Rm>\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);\r
      }\r
    }\r
\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0fb000f0) == 0x01000050) {\r
    // A4.1.108  SWP   SWP{<cond>}B <Rd>, <Rm>, [<Rn>]\r
    // A4.1.109  SWPB  SWP{<cond>}B <Rd>, <Rm>, [<Rn>]\r
    AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);\r
    return;\r
  }\r
\r
  if ((OpCode  & 0xfe5f0f00) == 0xf84d0500) {\r
    // A4.1.90 SRS SRS<addressing_mode> #<mode>{!}\r
    AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));\r
    return;\r
  }\r
\r
  if ((OpCode  & 0xfe500f00) == 0xf8100500) {\r
    // A4.1.59 RFE<addressing_mode> <Rn>{!}\r
    AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));\r
    return;\r
  }\r
\r
  if ((OpCode  & 0xfff000f0) == 0xe1200070) {\r
    // A4.1.7 BKPT <immed_16>\r
    AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);\r
    return;\r
  }\r
\r
  if ((OpCode  & 0xfff10020) == 0xf1000000) {\r
    // A4.1.16 CPS<effect> <iflags> {, #<mode>}\r
    if (((OpCode >> 6) & 0x7) == 0) {\r
      AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));\r
    } else {\r
      IMod  = (OpCode >> 18) & 0x3;\r
      Index = AsciiSPrint (\r
                Buf,\r
                Size,\r
                "CPS%a %a%a%a",\r
                (IMod == 3) ? "ID" : "IE",\r
                ((OpCode & BIT8) != 0) ? "A" : "",\r
                ((OpCode & BIT7) != 0) ? "I" : "",\r
                ((OpCode & BIT6) != 0) ? "F" : ""\r
                );\r
      if ((OpCode & BIT17) != 0) {\r
        AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);\r
      }\r
    }\r
\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0f000000) == 0x0f000000) {\r
    // A4.1.107 SWI{<cond>} <immed_24>\r
    AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0fb00000) == 0x01000000) {\r
    // A4.1.38 MRS{<cond>} <Rd>, CPSR  MRS{<cond>} <Rd>, SPSR\r
    AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0db00000) == 0x01200000) {\r
    // A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>\r
    if (Imm) {\r
      // MSR{<cond>} CPSR_<fields>, #<immediate>\r
      AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));\r
    } else {\r
      // MSR{<cond>} CPSR_<fields>, <Rm>\r
      AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);\r
    }\r
\r
    return;\r
  }\r
\r
  if ((OpCode  & 0xff000010) == 0xfe000000) {\r
    // A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>\r
    AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0e000000) == 0x0c000000) {\r
    // A4.1.19 LDC and A4.1.96 SDC\r
    if ((OpCode & 0xf0000000) == 0xf0000000) {\r
      Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);\r
    } else {\r
      Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
    }\r
\r
    if (!Pre) {\r
      if (!Write) {\r
        // A5.5.5.5 [<Rn>], <option>\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
      } else {\r
        // A.5.5.4  [<Rn>], #+/-<offset_8>*4\r
        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);\r
      }\r
    } else {\r
      // A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!\r
      AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));\r
    }\r
  }\r
\r
  if ((OpCode  & 0x0f000010) == 0x0e000010) {\r
    // A4.1.32 MRC2, MCR2\r
    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
    return;\r
  }\r
\r
  if ((OpCode  & 0x0ff00000) == 0x0c400000) {\r
    // A4.1.33 MRRC2, MCRR2\r
    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
    return;\r
  }\r
\r
  AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);\r
\r
  *OpCodePtr += 1;\r
  return;\r
}\r