[mirror_edk2.git] / ArmPkg / Library / ArmDisassemblerLib / ThumbDisassembler.c

/** @file\r
  Default exception handler\r
\r
  Copyright (c) 2008-2010, Apple Inc. All rights reserved.\r
  \r
  All rights reserved. This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Base.h>\r
#include <Library/BaseLib.h>\r
#include <Library/PrintLib.h>\r
\r
extern CHAR8 *gReg[];\r
\r
#define LOAD_STORE_FORMAT1            1\r
#define LOAD_STORE_FORMAT2            2\r
#define LOAD_STORE_FORMAT3            3\r
#define LOAD_STORE_FORMAT4            4\r
#define LOAD_STORE_MULTIPLE_FORMAT1   5 \r
#define LOAD_STORE_MULTIPLE_FORMAT2   6 \r
#define IMMED_8                       7\r
#define CONDITIONAL_BRANCH            8\r
#define UNCONDITIONAL_BRANCH          9\r
#define UNCONDITIONAL_BRANCH_SHORT  109\r
#define BRANCH_EXCHANGE              10\r
#define DATA_FORMAT1                 11\r
#define DATA_FORMAT2                 12\r
#define DATA_FORMAT3                 13\r
#define DATA_FORMAT4                 14\r
#define DATA_FORMAT5                 15\r
#define DATA_FORMAT6_SP              16\r
#define DATA_FORMAT6_PC             116\r
#define DATA_FORMAT7                 17\r
#define DATA_FORMAT8                 19\r
#define CPS_FORMAT                   20\r
#define ENDIAN_FORMAT                21\r
     \r
\r
typedef struct {\r
  CHAR8   *Start;\r
  UINT32  OpCode;\r
  UINT32  Mask;\r
  UINT32  AddressMode;\r
} THUMB_INSTRUCTIONS;\r
\r
THUMB_INSTRUCTIONS gOpThumb[] = {\r
// Thumb 16-bit instrucitons\r
//         Op      Mask    Format\r
  { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },\r
\r
  { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },\r
  { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },\r
  { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
  { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 },   // A8.6.9\r
  { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },\r
  { "ADD" , 0xa100, 0xf100, DATA_FORMAT6_SP }, \r
  { "ADD" , 0xb000, 0xff10, DATA_FORMAT7 },\r
\r
  { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },\r
\r
  { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },\r
  { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },\r
\r
  { "B"   , 0xd000, 0xf000, CONDITIONAL_BRANCH },\r
  { "B"   , 0xe000, 0xf100, UNCONDITIONAL_BRANCH_SHORT },\r
  { "BL"  , 0xf100, 0xf100, UNCONDITIONAL_BRANCH },\r
  { "BLX" , 0xe100, 0xf100, UNCONDITIONAL_BRANCH },\r
  { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },\r
  { "BX"  , 0x4700, 0xff80, BRANCH_EXCHANGE },\r
\r
  { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },\r
  { "BKPT", 0xdf00, 0xff00, IMMED_8 },\r
  { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },\r
\r
  { "CMP" , 0x2800, 0xf100, DATA_FORMAT3 },\r
  { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },\r
  { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },\r
\r
  { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },\r
  { "CPY" , 0x4600, 0xff00, DATA_FORMAT8 },\r
  { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },\r
\r
  { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
  { "LDR"   , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "LDR"   , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "LDR"   , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },\r
  { "LDR"   , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },\r
  { "LDRB"  , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "LDRB"  , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "LDRH"  , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "LDRH"  , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
 \r
  { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },\r
  { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },\r
  { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },\r
  { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },\r
\r
  { "MOV" , 0x2000, 0xf800, DATA_FORMAT3 },\r
  { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },\r
  { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },\r
\r
  { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },\r
  { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
  { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },\r
  { "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },\r
  { "POP" , 0xbc00, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },\r
  { "POP" , 0xe400, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },\r
  \r
  { "REV"   , 0xba00, 0xffc0, DATA_FORMAT5 },\r
  { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },\r
  { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },\r
\r
  { "ROR"  , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
  { "SBC"  , 0x4180, 0xffc0, DATA_FORMAT5 },\r
  { "SETEND"  , 0xb650, 0xfff0, ENDIAN_FORMAT },\r
\r
  { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
  { "STR"   , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "STR"   , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "STR"   , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },\r
  { "STR"   , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },\r
  { "STRB"  , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "STRB"  , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
  { "STRH"  , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },\r
  { "STRH"  , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },\r
\r
  { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },\r
  { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },\r
  { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },\r
  { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },\r
\r
  { "SWI" , 0xdf00, 0xff00, IMMED_8 },\r
  { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },\r
  { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },\r
  { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },\r
  { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },\r
  { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }\r
};\r
\r
#if 0  \r
THUMB_INSTRUCTIONS gOpThumb2[] = {\r
  ,\r
  \r
  // 32-bit Thumb instructions  op1 01\r
  \r
  //  1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple\r
  { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT },       // SRSDB<c> SP{!},#<mode>\r
  { "SRS"  , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT },    // SRS{IA}<c> SP{!},#<mode>\r
  { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT },       // RFEDB<c> <Rn>{!}\r
  { "RFE"  , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT },    // RFE{IA}<c> <Rn>{!}\r
  \r
  { "STM"  , 0xe8800000, 0xffd00000,  STM_FORMAT },      // STM<c>.W <Rn>{!},<registers>\r
  { "LDM"  , 0xe8900000, 0xffd00000,  STM_FORMAT },      // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
  { "POP"  , 0xe8bd0000, 0xffff2000,  REGLIST_FORMAT },  // POP<c>.W <registers> >1 register\r
  { "POP"  , 0xf85d0b04, 0xffff0fff,  RT_FORMAT },       // POP<c>.W <registers>  1 register\r
\r
  { "STMDB", 0xe9000000, 0xffd00000,  STM_FORMAT },      // STMDB\r
  { "PUSH" , 0xe8bd0000, 0xffffa000,  REGLIST_FORMAT },  // PUSH<c>.W <registers>  >1 register\r
  { "PUSH" , 0xf84d0b04, 0xffff0fff,  RT_FORMAT },       // PUSH<c>.W <registers>   1 register\r
  { "LDMDB", 0xe9102000, 0xffd02000,  STM_FORMAT },      // LDMDB<c> <Rn>{!},<registers>\r
\r
  //  1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,\r
  { "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT },  // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]\r
  { "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT },       // STREXB<c> <Rd>,<Rt>,[<Rn>]\r
  { "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT },       // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]\r
  { "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT },       // STREXH<c> <Rd>,<Rt>,[<Rn>]\r
  { "STRH",   0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT },  // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]\r
  { "STRH",   0xf8200000, 0xfff00000,  },                  // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
\r
\r
\r
  //  1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing\r
  //  1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor\r
  \r
  //  1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate\r
  //  1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate\r
  //  1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches\r
  \r
  //  1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item\r
  //  1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store\r
  //  1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints \r
  //  1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints\r
  //  1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word \r
\r
  //  1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register\r
  //  1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply\r
  //  1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply\r
  //  1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor \r
};\r
#endif\r
\r
CHAR8 mThumbMregListStr[4*15 + 1];\r
\r
CHAR8 *\r
ThumbMRegList (\r
  UINT32  OpCode\r
  )\r
{\r
  UINTN     Index, Start, End;\r
  CHAR8     *Str;\r
  BOOLEAN   First;\r
 \r
  Str = mThumbMregListStr;\r
  *Str = '\0';\r
  AsciiStrCat  (Str, "{");\r
  // R0 - R7, PC\r
  for (Index = 0, First = TRUE; Index <= 9; Index++) {\r
    if ((OpCode & (1 << Index)) != 0) {\r
      Start = End = Index;\r
      for (Index++; ((OpCode & (1 << Index)) != 0) && (Index <= 9); Index++) {\r
        End = Index;\r
      }\r
      \r
      if (!First) {\r
        AsciiStrCat  (Str, ",");\r
      } else {\r
        First = FALSE;\r
      }\r
      \r
      if (Start == End) {\r
        AsciiStrCat  (Str, gReg[(Start == 9)?15:Start]);\r
        AsciiStrCat  (Str, ", ");\r
      } else {\r
        AsciiStrCat  (Str, gReg[Start]);\r
        AsciiStrCat  (Str, "-");\r
        AsciiStrCat  (Str, gReg[(End == 9)?15:End]);\r
      }\r
    }\r
  }\r
  if (First) {\r
    AsciiStrCat  (Str, "ERROR");\r
  }\r
  AsciiStrCat  (Str, "}");\r
  \r
  // BugBug: Make caller pass in buffer it is cleaner\r
  return mThumbMregListStr;\r
}\r
\r
UINT32\r
SignExtend (\r
  IN  UINT32  Data\r
  )\r
{\r
  return 0;\r
}\r
\r
/**\r
  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
  point to next instructin. \r
  \r
  We cheat and only decode instructions that access \r
  memory. If the instruction is not found we dump the instruction in hex.\r
   \r
  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.  \r
  @param  Buf           Buffer to sprintf disassembly into.\r
  @param  Size          Size of Buf in bytes. \r
  @param  Extended    TRUE dump hex for instruction too.\r
  \r
**/\r
VOID\r
DisassembleThumbInstruction (\r
  IN  UINT16    **OpCodePtrPtr,\r
  OUT CHAR8     *Buf,\r
  OUT UINTN     Size,\r
  IN  BOOLEAN   Extended\r
  )\r
{\r
  UINT16  *OpCodePtr;\r
  UINT16  OpCode;\r
  UINT16  OpCode32;\r
  UINT32  Index;\r
  UINT32  Offset;\r
  UINT16  Rd, Rn, Rm;\r
  INT32   target_addr;\r
  BOOLEAN H1, H2, imod;\r
  UINT32  PC;\r
\r
  OpCodePtr = *OpCodePtrPtr;\r
  OpCode = **OpCodePtrPtr;\r
  \r
  // Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.\r
  OpCode32 = (OpCode << 16) | *(OpCodePtr + 1);\r
\r
  // These register names match branch form, but not others\r
  Rd = OpCode & 0x7;\r
  Rn = (OpCode >> 3) & 0x7;\r
  Rm = (OpCode >> 6) & 0x7;\r
  H1 = (OpCode & BIT7) != 0;\r
  H2 = (OpCode & BIT6) != 0;\r
  imod = (OpCode & BIT4) != 0;\r
  PC = (UINT32)(UINTN)*OpCodePtr;\r
\r
  // Increment by the minimum instruction size, Thumb2 could be bigger\r
  *OpCodePtrPtr += 1;\r
  \r
  for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
    if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {\r
      if (Extended) {\r
        Offset = AsciiSPrint (Buf, Size, "0x%04x       %a", OpCode, gOpThumb[Index].Start);   \r
      } else {\r
        Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb[Index].Start);   \r
      }\r
      switch (gOpThumb[Index].AddressMode) {\r
      case LOAD_STORE_FORMAT1:\r
        // A6.5.1  <Rd>, [<Rn>, #<5_bit_offset>]\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, (OpCode >> 7) & 7, (OpCode >> 6) & 0x1f);   \r
        break;\r
      case LOAD_STORE_FORMAT2:\r
        // A6.5.1  <Rd>, [<Rn>, <Rm>]\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, (OpCode >> 3) & 7, Rm);   \r
        break;\r
      case LOAD_STORE_FORMAT3:\r
        // A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);   \r
        break;\r
      case LOAD_STORE_FORMAT4:\r
        // FIX ME!!!!!\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);   \r
        break;\r
      \r
      case LOAD_STORE_MULTIPLE_FORMAT1:\r
        // <Rn>!, <registers>  \r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (!BIT8 & OpCode));   \r
        break;\r
      case LOAD_STORE_MULTIPLE_FORMAT2:\r
        // <Rn>!, <registers>  \r
        // BIT8 is PC \r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode));   \r
        break;\r
      \r
      case IMMED_8:\r
        // A6.7 <immed_8>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);   \r
        break;\r
\r
      case CONDITIONAL_BRANCH:\r
        // A6.3.1 B<cond> <target_address>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, "%a 0x%04x", PC + 4 + SignExtend ((OpCode & 0xff) << 1));   \r
        break;\r
      case UNCONDITIONAL_BRANCH_SHORT:\r
        // A6.3.2 B  <target_address>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend ((OpCode & 0x3ff) << 1));   \r
        break;\r
      case UNCONDITIONAL_BRANCH:\r
        // A6.3.2 BL|BLX <target_address>  ; Produces two 16-bit instructions \r
        target_addr = *(OpCodePtr - 1);\r
        if ((target_addr & 0xf800) == 0xf000) {\r
          target_addr = ((target_addr & 0x3ff) << 12) | (OpCode & 0x3ff);\r
        } else {\r
          target_addr = OpCode & 0x3ff;\r
        }\r
        // PC + 2 +/- target_addr\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 2 + SignExtend (target_addr));   \r
        break;\r
      case BRANCH_EXCHANGE:\r
        // A6.3.3 BX|BLX <Rm>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d", gReg[Rn | (H2 ? 8:0)]);   \r
        break;\r
\r
      case DATA_FORMAT1:\r
        // A6.4.3  <Rd>, <Rn>, <Rm>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);   \r
        break;\r
      case DATA_FORMAT2:\r
        // A6.4.3  <Rd>, <Rn>, #3_bit_immed\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);   \r
        break;\r
      case DATA_FORMAT3:\r
        // A6.4.3  <Rd>|<Rn>, #8_bit_immed\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", (OpCode >> 8) & 0x7, OpCode & 0xff);   \r
        break;\r
      case DATA_FORMAT4:\r
        // A6.4.3  <Rd>|<Rm>, #immed_5\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);   \r
        break;\r
      case DATA_FORMAT5:\r
        // A6.4.3  <Rd>|<Rm>, <Rm>|<Rs>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);   \r
        break;\r
      case DATA_FORMAT6_SP:\r
        // A6.4.3  <Rd>, <reg>, #<8_Bit_immed>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);   \r
        break;\r
      case DATA_FORMAT6_PC:\r
        // A6.4.3  <Rd>, <reg>, #<8_Bit_immed>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);   \r
        break;\r
      case DATA_FORMAT7:\r
        // A6.4.3  SP, SP, #<7_Bit_immed>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp 0x%x", (OpCode & 0x7f)*4);   \r
        break;\r
      case DATA_FORMAT8:\r
        // A6.4.3  <Rd>|<Rn>, <Rm>\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);   \r
        break;\r
      \r
      case CPS_FORMAT:\r
        // A7.1.24\r
        AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a",  ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");   \r
        break;\r
\r
      case ENDIAN_FORMAT:\r
        // A7.1.24\r
        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");   \r
        break;\r
      }\r
    }\r
  }\r
#if 0  \r
  // Thumb2 are 32-bit instructions\r
  *OpCodePtrPtr += 1;\r
  for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
    if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
      if (Extended) {\r
        Offset = AsciiSPrint (Buf, Size, "0x%04x   %a", OpCode32, gOpThumb2[Index].Start);   \r
      } else {\r
        Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb2[Index].Start);   \r
      }\r
      switch (gOpThumb2[Index].AddressMode) {\r
      }\r
    }\r
  }\r
#endif\r
  // Unknown instruction is 16-bits\r
  *OpCodePtrPtr -= 1;\r
  if (!Extended) {\r
    AsciiSPrint (Buf, Size, "0x%04x", OpCode);\r
  }\r
}\r
\r
\r
\r
VOID\r
DisassembleArmInstruction (\r
  IN  UINT32    **OpCodePtr,\r
  OUT CHAR8     *Buf,\r
  OUT UINTN     Size,\r
  IN  BOOLEAN   Extended\r
  );\r
\r
\r
/**\r
  Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
  point to next instructin. \r
  \r
  We cheat and only decode instructions that access \r
  memory. If the instruction is not found we dump the instruction in hex.\r
   \r
  @param  OpCodePtrPtr  Pointer to pointer of ARM Thumb instruction to disassemble.  \r
  @param  Thumb         TRUE for Thumb(2), FALSE for ARM instruction stream\r
  @param  Extended      TRUE dump hex for instruction too.\r
  @param  Buf           Buffer to sprintf disassembly into.\r
  @param  Size          Size of Buf in bytes. \r
  \r
**/\r
VOID\r
DisassembleInstruction (\r
  IN  UINT8     **OpCodePtr,\r
  IN  BOOLEAN   Thumb,\r
  IN  BOOLEAN   Extended,\r
  OUT CHAR8     *Buf,\r
  OUT UINTN     Size\r
  )\r
{\r
  if (Thumb) {\r
    DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, Extended);\r
  } else {\r
    DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);\r
  }\r
}\r
 \r
Commit	Line	Data
6f72e28d	1	/** @file\r
	2	Default exception handler\r
	3	\r
	4	Copyright (c) 2008-2010, Apple Inc. All rights reserved.\r
	5	\r
	6	All rights reserved. This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#include <Base.h>\r
	17	#include <Library/BaseLib.h>\r
	18	#include <Library/PrintLib.h>\r
	19	\r
	20	extern CHAR8 *gReg[];\r
	21	\r
	22	#define LOAD_STORE_FORMAT1 1\r
	23	#define LOAD_STORE_FORMAT2 2\r
	24	#define LOAD_STORE_FORMAT3 3\r
	25	#define LOAD_STORE_FORMAT4 4\r
	26	#define LOAD_STORE_MULTIPLE_FORMAT1 5 \r
	27	#define LOAD_STORE_MULTIPLE_FORMAT2 6 \r
	28	#define IMMED_8 7\r
	29	#define CONDITIONAL_BRANCH 8\r
	30	#define UNCONDITIONAL_BRANCH 9\r
	31	#define UNCONDITIONAL_BRANCH_SHORT 109\r
	32	#define BRANCH_EXCHANGE 10\r
	33	#define DATA_FORMAT1 11\r
	34	#define DATA_FORMAT2 12\r
	35	#define DATA_FORMAT3 13\r
	36	#define DATA_FORMAT4 14\r
	37	#define DATA_FORMAT5 15\r
	38	#define DATA_FORMAT6_SP 16\r
	39	#define DATA_FORMAT6_PC 116\r
	40	#define DATA_FORMAT7 17\r
	41	#define DATA_FORMAT8 19\r
	42	#define CPS_FORMAT 20\r
	43	#define ENDIAN_FORMAT 21\r
	44	\r
	45	\r
	46	typedef struct {\r
	47	CHAR8 *Start;\r
	48	UINT32 OpCode;\r
	49	UINT32 Mask;\r
	50	UINT32 AddressMode;\r
	51	} THUMB_INSTRUCTIONS;\r
	52	\r
097bd461	53	THUMB_INSTRUCTIONS gOpThumb[] = {\r
6f72e28d	54	// Thumb 16-bit instrucitons\r
	55	// Op Mask Format\r
	56	{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },\r
	57	\r
	58	{ "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },\r
	59	{ "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },\r
	60	{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
	61	{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9\r
	62	{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },\r
	63	{ "ADD" , 0xa100, 0xf100, DATA_FORMAT6_SP }, \r
	64	{ "ADD" , 0xb000, 0xff10, DATA_FORMAT7 },\r
	65	\r
	66	{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },\r
	67	\r
	68	{ "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },\r
	69	{ "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },\r
	70	\r
	71	{ "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },\r
	72	{ "B" , 0xe000, 0xf100, UNCONDITIONAL_BRANCH_SHORT },\r
	73	{ "BL" , 0xf100, 0xf100, UNCONDITIONAL_BRANCH },\r
	74	{ "BLX" , 0xe100, 0xf100, UNCONDITIONAL_BRANCH },\r
	75	{ "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },\r
	76	{ "BX" , 0x4700, 0xff80, BRANCH_EXCHANGE },\r
	77	\r
	78	{ "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },\r
	79	{ "BKPT", 0xdf00, 0xff00, IMMED_8 },\r
	80	{ "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },\r
	81	\r
	82	{ "CMP" , 0x2800, 0xf100, DATA_FORMAT3 },\r
	83	{ "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },\r
	84	{ "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },\r
	85	\r
	86	{ "CPS" , 0xb660, 0xffe8, CPS_FORMAT },\r
	87	{ "CPY" , 0x4600, 0xff00, DATA_FORMAT8 },\r
	88	{ "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },\r
	89	\r
	90	{ "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
	91	{ "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },\r
	92	{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
	93	{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },\r
	94	{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },\r
	95	{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },\r
	96	{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },\r
	97	{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },\r
	98	{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
	99	{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },\r
	100	{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
	101	\r
	102	{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },\r
	103	{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },\r
	104	{ "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },\r
	105	{ "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },\r
	106	\r
	107	{ "MOV" , 0x2000, 0xf800, DATA_FORMAT3 },\r
	108	{ "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },\r
	109	{ "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },\r
	110	\r
	111	{ "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },\r
	112	{ "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
	113	{ "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },\r
	114	{ "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },\r
	115	{ "POP" , 0xbc00, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },\r
	116	{ "POP" , 0xe400, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },\r
	117	\r
118	{ "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },\r
119	{ "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },\r
120	{ "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },\r
121	\r
122	{ "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },\r
123	{ "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },\r
124	{ "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },\r
125	\r
126	{ "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },\r
127	{ "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },\r
128	{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },\r
129	{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },\r
130	{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },\r
131	{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },\r
132	{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },\r
133	{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },\r
134	{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },\r
135	\r
136	{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },\r
137	{ "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },\r
138	{ "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },\r
139	{ "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },\r
140	\r
141	{ "SWI" , 0xdf00, 0xff00, IMMED_8 },\r
142	{ "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },\r
143	{ "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },\r
144	{ "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },\r
145	{ "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },\r
146	{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }\r
097bd461	147	};\r
097bd461	148	\r
6f72e28d	149	#if 0 \r
097bd461	150	THUMB_INSTRUCTIONS gOpThumb2[] = {\r
6f72e28d	151	,\r
	152	\r
	153	// 32-bit Thumb instructions op1 01\r
	154	\r
	155	// 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple\r
	156	{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
	157	{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
	158	{ "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}\r
	159	{ "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}\r
	160	\r
	161	{ "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>\r
	162	{ "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
	163	{ "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register\r
	164	{ "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register\r
	165	\r
	166	{ "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB\r
	167	{ "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register\r
	168	{ "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register\r
	169	{ "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>\r
	170	\r
	171	// 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,\r
	172	{ "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]\r
	173	{ "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]\r
	174	{ "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]\r
	175	{ "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]\r
	176	{ "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]\r
	177	{ "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]\r
	178	\r
	179	\r
	180	\r
	181	// 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing\r
	182	// 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor\r
	183	\r
	184	// 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate\r
	185	// 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate\r
	186	// 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches\r
	187	\r
	188	// 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item\r
	189	// 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store\r
	190	// 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints \r
	191	// 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints\r
	192	// 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word \r
	193	\r
	194	// 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register\r
	195	// 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply\r
	196	// 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply\r
	197	// 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor \r
6f72e28d	198	};\r
097bd461	199	#endif\r
6f72e28d	200	\r
	201	CHAR8 mThumbMregListStr[4*15 + 1];\r
	202	\r
	203	CHAR8 *\r
	204	ThumbMRegList (\r
	205	UINT32 OpCode\r
	206	)\r
	207	{\r
	208	UINTN Index, Start, End;\r
	209	CHAR8 *Str;\r
	210	BOOLEAN First;\r
	211	\r
	212	Str = mThumbMregListStr;\r
	213	*Str = '\0';\r
	214	AsciiStrCat (Str, "{");\r
	215	// R0 - R7, PC\r
	216	for (Index = 0, First = TRUE; Index <= 9; Index++) {\r
	217	if ((OpCode & (1 << Index)) != 0) {\r
	218	Start = End = Index;\r
	219	for (Index++; ((OpCode & (1 << Index)) != 0) && (Index <= 9); Index++) {\r
	220	End = Index;\r
	221	}\r
	222	\r
	223	if (!First) {\r
	224	AsciiStrCat (Str, ",");\r
	225	} else {\r
	226	First = FALSE;\r
	227	}\r
	228	\r
	229	if (Start == End) {\r
	230	AsciiStrCat (Str, gReg[(Start == 9)?15:Start]);\r
	231	AsciiStrCat (Str, ", ");\r
	232	} else {\r
	233	AsciiStrCat (Str, gReg[Start]);\r
	234	AsciiStrCat (Str, "-");\r
	235	AsciiStrCat (Str, gReg[(End == 9)?15:End]);\r
	236	}\r
	237	}\r
	238	}\r
	239	if (First) {\r
	240	AsciiStrCat (Str, "ERROR");\r
	241	}\r
	242	AsciiStrCat (Str, "}");\r
	243	\r
	244	// BugBug: Make caller pass in buffer it is cleaner\r
	245	return mThumbMregListStr;\r
	246	}\r
	247	\r
	248	UINT32\r
	249	SignExtend (\r
	250	IN UINT32 Data\r
	251	)\r
	252	{\r
	253	return 0;\r
	254	}\r
	255	\r
	256	/**\r
097bd461	257	Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
	258	point to next instructin. \r
	259	\r
	260	We cheat and only decode instructions that access \r
6f72e28d	261	memory. If the instruction is not found we dump the instruction in hex.\r
6f72e28d	262	\r
097bd461	263	@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
	264	@param Buf Buffer to sprintf disassembly into.\r
	265	@param Size Size of Buf in bytes. \r
f9f937d2	266	@param Extended TRUE dump hex for instruction too.\r
6f72e28d	267	\r
	268	**/\r
	269	VOID\r
	270	DisassembleThumbInstruction (\r
097bd461	271	IN UINT16 **OpCodePtrPtr,\r
6f72e28d	272	OUT CHAR8 *Buf,\r
f9f937d2	273	OUT UINTN Size,\r
f9f937d2	274	IN BOOLEAN Extended\r
6f72e28d	275	)\r
6f72e28d	276	{\r
097bd461	277	UINT16 *OpCodePtr;\r
	278	UINT16 OpCode;\r
	279	UINT16 OpCode32;\r
6f72e28d	280	UINT32 Index;\r
	281	UINT32 Offset;\r
	282	UINT16 Rd, Rn, Rm;\r
	283	INT32 target_addr;\r
	284	BOOLEAN H1, H2, imod;\r
	285	UINT32 PC;\r
	286	\r
097bd461	287	OpCodePtr = *OpCodePtrPtr;\r
	288	OpCode = **OpCodePtrPtr;\r
	289	\r
	290	// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.\r
	291	OpCode32 = (OpCode << 16) \| *(OpCodePtr + 1);\r
	292	\r
6f72e28d	293	// These register names match branch form, but not others\r
	294	Rd = OpCode & 0x7;\r
	295	Rn = (OpCode >> 3) & 0x7;\r
	296	Rm = (OpCode >> 6) & 0x7;\r
	297	H1 = (OpCode & BIT7) != 0;\r
	298	H2 = (OpCode & BIT6) != 0;\r
	299	imod = (OpCode & BIT4) != 0;\r
	300	PC = (UINT32)(UINTN)*OpCodePtr;\r
	301	\r
097bd461	302	// Increment by the minimum instruction size, Thumb2 could be bigger\r
	303	*OpCodePtrPtr += 1;\r
	304	\r
	305	for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
	306	if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {\r
f9f937d2	307	if (Extended) {\r
	308	Offset = AsciiSPrint (Buf, Size, "0x%04x %a", OpCode, gOpThumb[Index].Start); \r
	309	} else {\r
	310	Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb[Index].Start); \r
	311	}\r
097bd461	312	switch (gOpThumb[Index].AddressMode) {\r
6f72e28d	313	case LOAD_STORE_FORMAT1:\r
	314	// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
	315	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, (OpCode >> 7) & 7, (OpCode >> 6) & 0x1f); \r
	316	break;\r
	317	case LOAD_STORE_FORMAT2:\r
	318	// A6.5.1 <Rd>, [<Rn>, <Rm>]\r
	319	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, (OpCode >> 3) & 7, Rm); \r
	320	break;\r
	321	case LOAD_STORE_FORMAT3:\r
	322	// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
	323	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff); \r
	324	break;\r
	325	case LOAD_STORE_FORMAT4:\r
	326	// FIX ME!!!!!\r
	327	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff); \r
	328	break;\r
	329	\r
	330	case LOAD_STORE_MULTIPLE_FORMAT1:\r
	331	// <Rn>!, <registers> \r
	332	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (!BIT8 & OpCode)); \r
	333	break;\r
	334	case LOAD_STORE_MULTIPLE_FORMAT2:\r
	335	// <Rn>!, <registers> \r
	336	// BIT8 is PC \r
	337	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode)); \r
	338	break;\r
	339	\r
	340	case IMMED_8:\r
	341	// A6.7 <immed_8>\r
	342	AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff); \r
	343	break;\r
	344	\r
	345	case CONDITIONAL_BRANCH:\r
	346	// A6.3.1 B<cond> <target_address>\r
	347	AsciiSPrint (&Buf[Offset], Size - Offset, "%a 0x%04x", PC + 4 + SignExtend ((OpCode & 0xff) << 1)); \r
	348	break;\r
	349	case UNCONDITIONAL_BRANCH_SHORT:\r
	350	// A6.3.2 B <target_address>\r
	351	AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend ((OpCode & 0x3ff) << 1)); \r
	352	break;\r
	353	case UNCONDITIONAL_BRANCH:\r
	354	// A6.3.2 BL\|BLX <target_address> ; Produces two 16-bit instructions \r
	355	target_addr = *(OpCodePtr - 1);\r
	356	if ((target_addr & 0xf800) == 0xf000) {\r
	357	target_addr = ((target_addr & 0x3ff) << 12) \| (OpCode & 0x3ff);\r
	358	} else {\r
	359	target_addr = OpCode & 0x3ff;\r
	360	}\r
	361	// PC + 2 +/- target_addr\r
	362	AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 2 + SignExtend (target_addr)); \r
	363	break;\r
	364	case BRANCH_EXCHANGE:\r
	365	// A6.3.3 BX\|BLX <Rm>\r
	366	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d", gReg[Rn \| (H2 ? 8:0)]); \r
	367	break;\r
	368	\r
	369	case DATA_FORMAT1:\r
	370	// A6.4.3 <Rd>, <Rn>, <Rm>\r
	371	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm); \r
	372	break;\r
	373	case DATA_FORMAT2:\r
	374	// A6.4.3 <Rd>, <Rn>, #3_bit_immed\r
	375	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm); \r
	376	break;\r
377	case DATA_FORMAT3:\r
378	// A6.4.3 <Rd>\|<Rn>, #8_bit_immed\r
379	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", (OpCode >> 8) & 0x7, OpCode & 0xff); \r
380	break;\r
381	case DATA_FORMAT4:\r
382	// A6.4.3 <Rd>\|<Rm>, #immed_5\r
383	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f); \r
384	break;\r
385	case DATA_FORMAT5:\r
386	// A6.4.3 <Rd>\|<Rm>, <Rm>\|<Rs>\r
387	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn); \r
388	break;\r
389	case DATA_FORMAT6_SP:\r
390	// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
391	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff); \r
392	break;\r
393	case DATA_FORMAT6_PC:\r
394	// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
395	AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff); \r
396	break;\r
397	case DATA_FORMAT7:\r
398	// A6.4.3 SP, SP, #<7_Bit_immed>\r
399	AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp 0x%x", (OpCode & 0x7f)*4); \r
400	break;\r
401	case DATA_FORMAT8:\r
402	// A6.4.3 <Rd>\|<Rn>, <Rm>\r
403	AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd \| (H1 ? 8:0)], gReg[Rn \| (H2 ? 8:0)]); \r
404	break;\r
405	\r
406	case CPS_FORMAT:\r
407	// A7.1.24\r
408	AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f"); \r
409	break;\r
410	\r
411	case ENDIAN_FORMAT:\r
412	// A7.1.24\r
413	AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE"); \r
414	break;\r
415	}\r
416	}\r
417	}\r
097bd461	418	#if 0 \r
	419	// Thumb2 are 32-bit instructions\r
	420	*OpCodePtrPtr += 1;\r
	421	for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
	422	if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
f9f937d2	423	if (Extended) {\r
	424	Offset = AsciiSPrint (Buf, Size, "0x%04x %a", OpCode32, gOpThumb2[Index].Start); \r
	425	} else {\r
	426	Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb2[Index].Start); \r
	427	}\r
	428	switch (gOpThumb2[Index].AddressMode) {\r
	429	}\r
097bd461	430	}\r
	431	}\r
	432	#endif\r
	433	// Unknown instruction is 16-bits\r
	434	*OpCodePtrPtr -= 1;\r
f9f937d2	435	if (!Extended) {\r
	436	AsciiSPrint (Buf, Size, "0x%04x", OpCode);\r
	437	}\r
6f72e28d	438	}\r
6f72e28d	439	\r
097bd461	440	\r
	441	\r
	442	VOID\r
	443	DisassembleArmInstruction (\r
	444	IN UINT32 **OpCodePtr,\r
	445	OUT CHAR8 *Buf,\r
f9f937d2	446	OUT UINTN Size,\r
f9f937d2	447	IN BOOLEAN Extended\r
097bd461	448	);\r
	449	\r
	450	\r
	451	/**\r
	452	Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
	453	point to next instructin. \r
	454	\r
	455	We cheat and only decode instructions that access \r
	456	memory. If the instruction is not found we dump the instruction in hex.\r
	457	\r
	458	@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
	459	@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream\r
f9f937d2	460	@param Extended TRUE dump hex for instruction too.\r
097bd461	461	@param Buf Buffer to sprintf disassembly into.\r
	462	@param Size Size of Buf in bytes. \r
	463	\r
	464	**/\r
	465	VOID\r
	466	DisassembleInstruction (\r
	467	IN UINT8 **OpCodePtr,\r
	468	IN BOOLEAN Thumb,\r
f9f937d2	469	IN BOOLEAN Extended,\r
097bd461	470	OUT CHAR8 *Buf,\r
	471	OUT UINTN Size\r
	472	)\r
	473	{\r
	474	if (Thumb) {\r
f9f937d2	475	DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, Extended);\r
097bd461	476	} else {\r
f9f937d2	477	DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);\r
097bd461	478	}\r
097bd461	479	}\r
6f72e28d	480	\r