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2939c778 EC |
1 | /** @file\r |
2 | * Exception Handling support specific for AArch64\r | |
3 | *\r | |
4 | * Copyright (c) 2016 HP Development Company, L.P.\r | |
74b41d56 | 5 | * Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r |
2939c778 | 6 | *\r |
4059386c | 7 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
2939c778 EC |
8 | *\r |
9 | **/\r | |
10 | \r | |
11 | #include <Uefi.h>\r | |
12 | \r | |
13 | #include <Chipset/AArch64.h>\r | |
2d120489 | 14 | #include <Library/MemoryAllocationLib.h>\r |
2939c778 EC |
15 | #include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION\r |
16 | \r | |
17 | UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;\r | |
18 | EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };\r | |
19 | EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };\r | |
20 | PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;\r | |
21 | UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64\r | |
22 | \r | |
e1d24410 HG |
23 | #define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)\r |
24 | STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];\r | |
2d120489 AB |
25 | \r |
26 | VOID\r | |
27 | RegisterEl0Stack (\r | |
28 | IN VOID *Stack\r | |
29 | );\r | |
30 | \r | |
74b41d56 PG |
31 | RETURN_STATUS\r |
32 | ArchVectorConfig (\r | |
2939c778 EC |
33 | IN UINTN VectorBaseAddress\r |
34 | )\r | |
35 | {\r | |
36 | UINTN HcrReg;\r | |
2d120489 | 37 | \r |
e1d24410 HG |
38 | // Round down sp by 16 bytes alignment\r |
39 | RegisterEl0Stack (\r | |
40 | (VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)\r | |
41 | );\r | |
2939c778 EC |
42 | \r |
43 | if (ArmReadCurrentEL() == AARCH64_EL2) {\r | |
44 | HcrReg = ArmReadHcr();\r | |
45 | \r | |
46 | // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2\r | |
47 | HcrReg |= ARM_HCR_TGE;\r | |
48 | \r | |
49 | ArmWriteHcr(HcrReg);\r | |
50 | }\r | |
51 | \r | |
52 | return RETURN_SUCCESS;\r | |
53 | }\r |