ArmPkg: use ID register helper for ArmGicArch(Sec)Lib

[mirror_edk2.git] / ArmPkg / Library / ArmGicArchLib / Arm / ArmGicArchLib.c

/** @file\r
*\r
*  Copyright (c) 2014, ARM Limited. All rights reserved.\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
STATIC ARM_GIC_ARCH_REVISION        mGicArchRevision;\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmGicArchLibInitialize (\r
  VOID\r
  )\r
{\r
  UINT32    IccSre;\r
\r
  // Ideally we would like to use the GICC IIDR Architecture version here, but\r
  // this does not seem to be very reliable as the implementation could easily\r
  // get it wrong. It is more reliable to check if the GICv3 System Register\r
  // feature is implemented on the CPU. This is also convenient as our GICv3\r
  // driver requires SRE. If only Memory mapped access is available we try to\r
  // drive the GIC as a v2.\r
  if (ArmHasGicSystemRegisters ()) {\r
    // Make sure System Register access is enabled (SRE). This depends on the\r
    // higher privilege level giving us permission, otherwise we will either\r
    // cause an exception here, or the write doesn't stick in which case we need\r
    // to fall back to the GICv2 MMIO interface.\r
    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r
    // at the same exception level.\r
    // It is the OS responsibility to set this bit.\r
    IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
    if (!(IccSre & ICC_SRE_EL2_SRE)) {\r
      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);\r
      IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r
    }\r
    if (IccSre & ICC_SRE_EL2_SRE) {\r
      mGicArchRevision = ARM_GIC_ARCH_REVISION_3;\r
      goto Done;\r
    }\r
  }\r
\r
  mGicArchRevision = ARM_GIC_ARCH_REVISION_2;\r
\r
Done:\r
  return RETURN_SUCCESS;\r
}\r
\r
ARM_GIC_ARCH_REVISION\r
EFIAPI\r
ArmGicGetSupportedArchRevision (\r
  VOID\r
  )\r
{\r
  return mGicArchRevision;\r
}\r