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e9e9c7e8 AB |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
4059386c | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e9e9c7e8 AB |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #include <Library/ArmLib.h>\r | |
10 | #include <Library/ArmGicLib.h>\r | |
11 | \r | |
12 | ARM_GIC_ARCH_REVISION\r | |
13 | EFIAPI\r | |
14 | ArmGicGetSupportedArchRevision (\r | |
15 | VOID\r | |
16 | )\r | |
17 | {\r | |
429309e0 | 18 | UINT32 IccSre;\r |
e9e9c7e8 AB |
19 | \r |
20 | // Ideally we would like to use the GICC IIDR Architecture version here, but\r | |
21 | // this does not seem to be very reliable as the implementation could easily\r | |
22 | // get it wrong. It is more reliable to check if the GICv3 System Register\r | |
23 | // feature is implemented on the CPU. This is also convenient as our GICv3\r | |
24 | // driver requires SRE. If only Memory mapped access is available we try to\r | |
25 | // drive the GIC as a v2.\r | |
b7ae5efb | 26 | if (ArmHasGicSystemRegisters ()) {\r |
e9e9c7e8 AB |
27 | // Make sure System Register access is enabled (SRE). This depends on the\r |
28 | // higher privilege level giving us permission, otherwise we will either\r | |
29 | // cause an exception here, or the write doesn't stick in which case we need\r | |
30 | // to fall back to the GICv2 MMIO interface.\r | |
31 | // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r | |
32 | // at the same exception level.\r | |
33 | // It is the OS responsibility to set this bit.\r | |
34 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r | |
35 | if (!(IccSre & ICC_SRE_EL2_SRE)) {\r | |
36 | ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r | |
37 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r | |
38 | }\r | |
429309e0 | 39 | \r |
e9e9c7e8 AB |
40 | if (IccSre & ICC_SRE_EL2_SRE) {\r |
41 | return ARM_GIC_ARCH_REVISION_3;\r | |
42 | }\r | |
43 | }\r | |
44 | \r | |
45 | return ARM_GIC_ARCH_REVISION_2;\r | |
46 | }\r |