projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 25402f5d HL |
1 | #------------------------------------------------------------------------------\r |
| 2 | #\r | |
| 3 | # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r | |
| 4 | #\r | |
| 5 | # This program and the accompanying materials\r | |
| 6 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | # http://opensource.org/licenses/bsd-license.php\r | |
| 9 | #\r | |
| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | #\r | |
| 13 | #------------------------------------------------------------------------------\r | |
| 14 | \r | |
| 15 | .text\r | |
| 16 | .align 2\r | |
| 17 | \r | |
| 919a3a02 BJ |
18 | GCC_ASM_EXPORT(ArmReadCntFrq)\r |
| 19 | GCC_ASM_EXPORT(ArmWriteCntFrq)\r | |
| 20 | GCC_ASM_EXPORT(ArmReadCntPct)\r | |
| 21 | GCC_ASM_EXPORT(ArmReadCntkCtl)\r | |
| 22 | GCC_ASM_EXPORT(ArmWriteCntkCtl)\r | |
| 23 | GCC_ASM_EXPORT(ArmReadCntpTval)\r | |
| 24 | GCC_ASM_EXPORT(ArmWriteCntpTval)\r | |
| 25 | GCC_ASM_EXPORT(ArmReadCntpCtl)\r | |
| 26 | GCC_ASM_EXPORT(ArmWriteCntpCtl)\r | |
| 27 | GCC_ASM_EXPORT(ArmReadCntvTval)\r | |
| 28 | GCC_ASM_EXPORT(ArmWriteCntvTval)\r | |
| 29 | GCC_ASM_EXPORT(ArmReadCntvCtl)\r | |
| 30 | GCC_ASM_EXPORT(ArmWriteCntvCtl)\r | |
| 31 | GCC_ASM_EXPORT(ArmReadCntvCt)\r | |
| 32 | GCC_ASM_EXPORT(ArmReadCntpCval)\r | |
| 33 | GCC_ASM_EXPORT(ArmWriteCntpCval)\r | |
| 34 | GCC_ASM_EXPORT(ArmReadCntvCval)\r | |
| 35 | GCC_ASM_EXPORT(ArmWriteCntvCval)\r | |
| 36 | GCC_ASM_EXPORT(ArmReadCntvOff)\r | |
| 37 | GCC_ASM_EXPORT(ArmWriteCntvOff)\r | |
| 25402f5d HL |
38 | \r |
| 39 | ASM_PFX(ArmReadCntFrq):\r | |
| 40 | mrs x0, cntfrq_el0 // Read CNTFRQ\r | |
| 41 | ret\r | |
| 42 | \r | |
| 43 | \r | |
| 44 | # NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0)\r | |
| 45 | ASM_PFX(ArmWriteCntFrq):\r | |
| 46 | msr cntfrq_el0, x0 // Write to CNTFRQ\r | |
| 47 | ret\r | |
| 48 | \r | |
| 49 | \r | |
| 50 | ASM_PFX(ArmReadCntPct):\r | |
| 51 | mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register)\r | |
| 52 | ret\r | |
| 53 | \r | |
| 54 | \r | |
| 55 | ASM_PFX(ArmReadCntkCtl):\r | |
| 56 | mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register)\r | |
| 57 | ret\r | |
| 58 | \r | |
| 59 | \r | |
| 60 | ASM_PFX(ArmWriteCntkCtl):\r | |
| 61 | mrs x0, cntkctl_el1 // Write to CNTK_CTL (Timer PL1 Control Register)\r | |
| 62 | ret\r | |
| 63 | \r | |
| 64 | \r | |
| 65 | ASM_PFX(ArmReadCntpTval):\r | |
| 66 | mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register)\r | |
| 67 | ret\r | |
| 68 | \r | |
| 69 | \r | |
| 70 | ASM_PFX(ArmWriteCntpTval):\r | |
| 71 | msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register)\r | |
| 72 | ret\r | |
| 73 | \r | |
| 74 | \r | |
| 75 | ASM_PFX(ArmReadCntpCtl):\r | |
| 76 | mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register)\r | |
| 77 | ret\r | |
| 78 | \r | |
| 79 | \r | |
| 80 | ASM_PFX(ArmWriteCntpCtl):\r | |
| 81 | msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register)\r | |
| 82 | ret\r | |
| 83 | \r | |
| 84 | \r | |
| 85 | ASM_PFX(ArmReadCntvTval):\r | |
| 86 | mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register)\r | |
| 87 | ret\r | |
| 88 | \r | |
| 89 | \r | |
| 90 | ASM_PFX(ArmWriteCntvTval):\r | |
| 91 | msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register)\r | |
| 92 | ret\r | |
| 93 | \r | |
| 94 | \r | |
| 95 | ASM_PFX(ArmReadCntvCtl):\r | |
| 96 | mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register)\r | |
| 97 | ret\r | |
| 98 | \r | |
| 99 | \r | |
| 100 | ASM_PFX(ArmWriteCntvCtl):\r | |
| 101 | msr cntv_ctl_el0, x0 // Write to CNTV_CTL (Virtual Timer Control Register)\r | |
| 102 | ret\r | |
| 103 | \r | |
| 104 | \r | |
| 105 | ASM_PFX(ArmReadCntvCt):\r | |
| 106 | mrs x0, cntvct_el0 // Read CNTVCT (Virtual Count Register)\r | |
| 107 | ret\r | |
| 108 | \r | |
| 109 | \r | |
| 110 | ASM_PFX(ArmReadCntpCval):\r | |
| 111 | mrs x0, cntp_cval_el0 // Read CNTP_CTVAL (Physical Timer Compare Value Register)\r | |
| 112 | ret\r | |
| 113 | \r | |
| 114 | \r | |
| 115 | ASM_PFX(ArmWriteCntpCval):\r | |
| 116 | msr cntp_cval_el0, x0 // Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r | |
| 117 | ret\r | |
| 118 | \r | |
| 119 | \r | |
| 120 | ASM_PFX(ArmReadCntvCval):\r | |
| 121 | mrs x0, cntv_cval_el0 // Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r | |
| 122 | ret\r | |
| 123 | \r | |
| 124 | \r | |
| 125 | ASM_PFX(ArmWriteCntvCval):\r | |
| 126 | msr cntv_cval_el0, x0 // write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r | |
| 127 | ret\r | |
| 128 | \r | |
| 129 | \r | |
| 130 | ASM_PFX(ArmReadCntvOff):\r | |
| 131 | mrs x0, cntvoff_el2 // Read CNTVOFF (virtual Offset register)\r | |
| 132 | ret\r | |
| 133 | \r | |
| 134 | \r | |
| 135 | ASM_PFX(ArmWriteCntvOff):\r | |
| 136 | msr cntvoff_el2, x0 // Write to CNTVOFF (Virtual Offset register)\r | |
| 137 | ret\r | |
| 138 | \r | |
| 139 | \r | |
| 140 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |