ArmPkg/ArmLib: AARCH64: set frame pointer in cache maintenance routine

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / ArmLibSupportV8.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <AsmMacroIoLibV8.h>\r
\r
.set MPIDR_U_BIT,    (30)\r
.set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)\r
\r
// DAIF bit definitions for writing through msr daifclr/sr daifset\r
.set DAIF_WR_FIQ_BIT,   (1 << 0)\r
.set DAIF_WR_IRQ_BIT,   (1 << 1)\r
.set DAIF_WR_ABORT_BIT, (1 << 2)\r
.set DAIF_WR_DEBUG_BIT, (1 << 3)\r
.set DAIF_WR_INT_BITS,  (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)\r
.set DAIF_WR_ALL,       (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r
\r
\r
ASM_FUNC(ArmIsMpCore)\r
  mrs   x0, mpidr_el1         // Read EL1 Mutliprocessor Affinty Reg (MPIDR)\r
  and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r
  lsr   x0, x0, #MPIDR_U_BIT\r
  eor   x0, x0, #1\r
  ret\r
\r
\r
ASM_FUNC(ArmEnableAsynchronousAbort)\r
  msr   daifclr, #DAIF_WR_ABORT_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmDisableAsynchronousAbort)\r
  msr   daifset, #DAIF_WR_ABORT_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmEnableIrq)\r
  msr   daifclr, #DAIF_WR_IRQ_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmDisableIrq)\r
  msr   daifset, #DAIF_WR_IRQ_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmEnableFiq)\r
  msr   daifclr, #DAIF_WR_FIQ_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmDisableFiq)\r
  msr   daifset, #DAIF_WR_FIQ_BIT\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmEnableInterrupts)\r
  msr   daifclr, #DAIF_WR_INT_BITS\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmDisableInterrupts)\r
  msr   daifset, #DAIF_WR_INT_BITS\r
  isb\r
  ret\r
\r
\r
ASM_FUNC(ArmDisableAllExceptions)\r
  msr   daifset, #DAIF_WR_ALL\r
  isb\r
  ret\r
\r
\r
// UINT32\r
// ReadCCSIDR (\r
//   IN UINT32 CSSELR\r
//   )\r
ASM_FUNC(ReadCCSIDR)\r
  msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)\r
  isb\r
  mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)\r
  ret\r
\r
\r
// UINT32\r
// ReadCLIDR (\r
//   IN UINT32 CSSELR\r
//   )\r
ASM_FUNC(ReadCLIDR)\r
  mrs   x0, clidr_el1         // Read Cache Level ID Register\r
  ret\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r