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Commit | Line | Data |
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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
5cc25cff | 5 | Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r |
3402aac7 | 6 | \r |
4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 8 | \r |
9 | **/\r | |
b58ec859 AB |
10 | \r |
11 | #include <Base.h>\r | |
12 | \r | |
1e57a462 | 13 | #include <Library/ArmLib.h>\r |
a2ab46ad | 14 | #include <Library/DebugLib.h>\r |
b58ec859 AB |
15 | \r |
16 | #include <Chipset/ArmV7.h>\r | |
17 | \r | |
1e57a462 | 18 | #include "ArmV7Lib.h"\r |
19 | #include "ArmLibPrivate.h"\r | |
20 | \r | |
1e57a462 | 21 | VOID\r |
22 | ArmV7DataCacheOperation (\r | |
23 | IN ARM_V7_CACHE_OPERATION DataCacheOperation\r | |
24 | )\r | |
25 | {\r | |
26 | UINTN SavedInterruptState;\r | |
27 | \r | |
28 | SavedInterruptState = ArmGetInterruptState ();\r | |
29 | ArmDisableInterrupts ();\r | |
3402aac7 | 30 | \r |
1e57a462 | 31 | ArmV7AllDataCachesOperation (DataCacheOperation);\r |
3402aac7 | 32 | \r |
3b149515 | 33 | ArmDataSynchronizationBarrier ();\r |
3402aac7 | 34 | \r |
1e57a462 | 35 | if (SavedInterruptState) {\r |
36 | ArmEnableInterrupts ();\r | |
37 | }\r | |
38 | }\r | |
39 | \r | |
1e57a462 | 40 | VOID\r |
41 | EFIAPI\r | |
42 | ArmInvalidateDataCache (\r | |
43 | VOID\r | |
44 | )\r | |
45 | {\r | |
a2ab46ad AB |
46 | ASSERT (!ArmMmuEnabled ());\r |
47 | \r | |
3b149515 | 48 | ArmDataSynchronizationBarrier ();\r |
1e57a462 | 49 | ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r |
50 | }\r | |
51 | \r | |
52 | VOID\r | |
53 | EFIAPI\r | |
54 | ArmCleanInvalidateDataCache (\r | |
55 | VOID\r | |
56 | )\r | |
57 | {\r | |
a2ab46ad AB |
58 | ASSERT (!ArmMmuEnabled ());\r |
59 | \r | |
3b149515 | 60 | ArmDataSynchronizationBarrier ();\r |
1e57a462 | 61 | ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r |
62 | }\r | |
63 | \r | |
64 | VOID\r | |
65 | EFIAPI\r | |
66 | ArmCleanDataCache (\r | |
67 | VOID\r | |
68 | )\r | |
69 | {\r | |
a2ab46ad AB |
70 | ASSERT (!ArmMmuEnabled ());\r |
71 | \r | |
3b149515 | 72 | ArmDataSynchronizationBarrier ();\r |
1e57a462 | 73 | ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
74 | }\r | |
5cc25cff LL |
75 | \r |
76 | /**\r | |
77 | Check whether the CPU supports the GIC system register interface (any version)\r | |
78 | \r | |
79 | @return Whether GIC System Register Interface is supported\r | |
80 | \r | |
81 | **/\r | |
82 | BOOLEAN\r | |
83 | EFIAPI\r | |
84 | ArmHasGicSystemRegisters (\r | |
85 | VOID\r | |
86 | )\r | |
87 | {\r | |
88 | return ((ArmReadIdPfr1 () & ARM_PFR1_GIC) != 0);\r | |
89 | }\r | |
740b870d LL |
90 | \r |
91 | /**\r | |
92 | Check whether the CPU supports the Security extensions\r | |
93 | \r | |
94 | @return Whether the Security extensions are implemented\r | |
95 | \r | |
96 | **/\r | |
97 | BOOLEAN\r | |
98 | EFIAPI\r | |
99 | ArmHasSecurityExtensions (\r | |
100 | VOID\r | |
101 | )\r | |
102 | {\r | |
103 | return ((ArmReadIdPfr1 () & ARM_PFR1_SEC) != 0);\r | |
104 | }\r |