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0c0e7ef4 | 1 | /** @file |
2 | ||
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #include <Chipset/ARM1176JZ-S.h> | |
16 | #include <Library/ArmLib.h> | |
17 | #include <Library/BaseMemoryLib.h> | |
18 | #include <Library/MemoryAllocationLib.h> | |
19 | ||
20 | VOID | |
21 | FillTranslationTable ( | |
22 | IN UINT32 *TranslationTable, | |
23 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion | |
24 | ) | |
25 | { | |
26 | UINT32 *Entry; | |
27 | UINTN Sections; | |
28 | UINTN Index; | |
29 | UINT32 Attributes; | |
30 | UINT32 PhysicalBase = MemoryRegion->PhysicalBase; | |
31 | ||
32 | switch (MemoryRegion->Attributes) { | |
33 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: | |
34 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); | |
35 | break; | |
36 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: | |
37 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); | |
38 | break; | |
39 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: | |
40 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); | |
41 | break; | |
7fffeef9 | 42 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: |
0c0e7ef4 | 43 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); |
44 | break; | |
7fffeef9 | 45 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: |
0c0e7ef4 | 46 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); |
47 | break; | |
7fffeef9 | 48 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: |
0c0e7ef4 | 49 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); |
50 | break; | |
51 | default: | |
52 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); | |
53 | break; | |
54 | } | |
55 | ||
56 | Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); | |
57 | Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 ); | |
58 | ||
59 | for (Index = 0; Index < Sections; Index++) | |
60 | { | |
61 | *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes; | |
62 | PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; | |
63 | } | |
64 | } | |
65 | ||
66 | VOID | |
67 | EFIAPI | |
68 | ArmConfigureMmu ( | |
69 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
70 | OUT VOID **TranslationTableBase OPTIONAL, | |
71 | OUT UINTN *TranslationTableSize OPTIONAL | |
72 | ) | |
73 | { | |
74 | VOID *TranslationTable; | |
75 | ||
76 | // Allocate pages for translation table. | |
77 | TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT)); | |
78 | TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK); | |
79 | ||
80 | if (TranslationTableBase != NULL) { | |
81 | *TranslationTableBase = TranslationTable; | |
82 | } | |
83 | ||
84 | if (TranslationTableBase != NULL) { | |
85 | *TranslationTableSize = TRANSLATION_TABLE_SIZE; | |
86 | } | |
87 | ||
88 | ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE); | |
89 | ||
90 | ArmCleanInvalidateDataCache(); | |
91 | ArmInvalidateInstructionCache(); | |
92 | ArmInvalidateTlb(); | |
93 | ||
94 | ArmDisableDataCache(); | |
95 | ArmDisableInstructionCache(); | |
96 | ArmDisableMmu(); | |
97 | ||
98 | // Make sure nothing sneaked into the cache | |
99 | ArmCleanInvalidateDataCache(); | |
100 | ArmInvalidateInstructionCache(); | |
101 | ||
102 | while (MemoryTable->Length != 0) { | |
103 | FillTranslationTable(TranslationTable, MemoryTable); | |
104 | MemoryTable++; | |
105 | } | |
106 | ||
107 | ArmSetTTBR0(TranslationTable); | |
108 | ||
109 | ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) | | |
110 | DOMAIN_ACCESS_CONTROL_NONE(14) | | |
111 | DOMAIN_ACCESS_CONTROL_NONE(13) | | |
112 | DOMAIN_ACCESS_CONTROL_NONE(12) | | |
113 | DOMAIN_ACCESS_CONTROL_NONE(11) | | |
114 | DOMAIN_ACCESS_CONTROL_NONE(10) | | |
115 | DOMAIN_ACCESS_CONTROL_NONE( 9) | | |
116 | DOMAIN_ACCESS_CONTROL_NONE( 8) | | |
117 | DOMAIN_ACCESS_CONTROL_NONE( 7) | | |
118 | DOMAIN_ACCESS_CONTROL_NONE( 6) | | |
119 | DOMAIN_ACCESS_CONTROL_NONE( 5) | | |
120 | DOMAIN_ACCESS_CONTROL_NONE( 4) | | |
121 | DOMAIN_ACCESS_CONTROL_NONE( 3) | | |
122 | DOMAIN_ACCESS_CONTROL_NONE( 2) | | |
123 | DOMAIN_ACCESS_CONTROL_NONE( 1) | | |
124 | DOMAIN_ACCESS_CONTROL_MANAGER(0)); | |
125 | ||
126 | ArmEnableInstructionCache(); | |
127 | ArmEnableDataCache(); | |
128 | ArmEnableMmu(); | |
129 | } | |
130 | ||
131 | ||
132 | ||
133 |