[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.S

#------------------------------------------------------------------------------ 
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution.  The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------

#include <AsmMacroIoLib.h>

.text
.align 2
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT(ArmSetLowVectors)
GCC_ASM_EXPORT(ArmSetHighVectors)
GCC_ASM_EXPORT(ArmIsMpCore)
GCC_ASM_EXPORT(ArmCallWFI)
GCC_ASM_EXPORT(ArmReadMpidr)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT (ArmEnableVFP)

Arm11PartNumberMask:  .word       0xFFF0
Arm11PartNumber:      .word	      0xB020

.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)
.set XP_ON, (0x1<<23)
.set CTRL_M_BIT,  (1 << 0)
.set CTRL_C_BIT,  (1 << 2)
.set CTRL_I_BIT,  (1 << 12)

ASM_PFX(ArmDisableCachesAndMmu):
  mrc   p15, 0, r0, c1, c0, 0           @ Get control register
  bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
  bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
  bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
  mcr   p15, 0, r0, c1, c0, 0           @ Write control register
  bx      LR

ASM_PFX(ArmInvalidateInstructionAndDataTlb):
  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
  bx lr

ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           
  bx      lr


ASM_PFX(ArmCleanDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  bx      lr


ASM_PFX(ArmCleanDataCache):
  mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCache):
  mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  bx      lr


ASM_PFX(ArmInvalidateDataCache):
  mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
  bx      lr


ASM_PFX(ArmInvalidateInstructionCache):
  mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
  bx      lr

ASM_PFX(ArmEnableMmu):
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ASM_PFX(ArmMmuEnabled):
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR

ASM_PFX(ArmDisableMmu):
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
  bx      LR

ASM_PFX(ArmEnableDataCache):
  LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  orr     R0,R0,R1              @Set C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  bx      LR
    
ASM_PFX(ArmDisableDataCache):
  LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  bic     R0,R0,R1              @Clear C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  bx      LR

ASM_PFX(ArmEnableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
  orr     R0,R0,R1             @Set I bit
  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
  bx      LR
  
ASM_PFX(ArmDisableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
  bic     R0,R0,R1             @Clear I bit.
  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
  bx      LR

ASM_PFX(ArmEnableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

ASM_PFX(ArmDisableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

ASM_PFX(ArmDataMemoryBarrier):
  mov R0, #0
  mcr P15, #0, R0, C7, C10, #5 
  bx      LR
  
ASM_PFX(ArmDataSyncronizationBarrier):
  mov R0, #0
  mcr P15, #0, R0, C7, C10, #4 
  bx      LR
  
ASM_PFX(ArmInstructionSynchronizationBarrier):
  mov R0, #0
  mcr P15, #0, R0, C7, C5, #4 
  bx      LR

ASM_PFX(ArmSetLowVectors):
  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
  bic     r0, r0, #0x00002000   @ clear V bit
  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
  bx      LR

ASM_PFX(ArmSetHighVectors):
  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
  orr     r0, r0, #0x00002000   @ clear V bit
  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
  bx      LR

ASM_PFX(ArmIsMpCore):
  push    { r1 }
  mrc     p15, 0, r0, c0, c0, 0
  # Extract Part Number to check it is an ARM11MP core (0xB02)
  LoadConstantToReg (Arm11PartNumberMask, r1)
  and     r0, r0, r1
  LoadConstantToReg (Arm11PartNumber, r1)
  cmp     r0, r1
  movne   r0, #0
  pop     { r1 }
  bx      lr     

ASM_PFX(ArmCallWFI):
  wfi
  bx      lr

ASM_PFX(ArmReadMpidr):
  mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
  bx      lr

ASM_PFX(ArmEnableFiq):
  mrs     R0,CPSR
  bic     R0,R0,#0x40    @Enable FIQ interrupts
  msr     CPSR_c,R0
  bx      LR

ASM_PFX(ArmDisableFiq):
  mrs     R0,CPSR
  orr     R1,R0,#0x40    @Disable FIQ interrupts
  msr     CPSR_c,R1
  tst     R0,#0x80
  moveq   R0,#1
  movne   R0,#0
  bx      LR

ASM_PFX(ArmEnableInterrupts):
  mrs     R0,CPSR
  bic     R0,R0,#0x80    @Enable IRQ interrupts
  msr     CPSR_c,R0
  bx      LR

ASM_PFX(ArmDisableInterrupts):
  mrs     R0,CPSR
  orr     R1,R0,#0x80    @Disable IRQ interrupts
  msr     CPSR_c,R1
  tst     R0,#0x80
  moveq   R0,#1
  movne   R0,#0
  bx      LR

ASM_PFX(ArmEnableVFP):
  # Read CPACR (Coprocessor Access Control Register)
  mrc     p15, 0, r0, c1, c0, 2
  # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
  orr     r0, r0, #0x00f00000
  # Write back CPACR (Coprocessor Access Control Register)
  mcr     p15, 0, r0, c1, c0, 2
  # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
  mov     r0, #0x40000000
  #TODO: Fixme - need compilation flag
  #fmxr    FPEXC, r0
  bx      lr

ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
2ef2b01e A	1	#------------------------------------------------------------------------------
2ef2b01e A	2	#
d6ebcab7	3	# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
0c0e7ef4	4	# Copyright (c) 2011, ARM Limited. All rights reserved.
2ef2b01e	5	#
d6ebcab7	6	# This program and the accompanying materials
2ef2b01e A	7	# are licensed and made available under the terms and conditions of the BSD License
	8	# which accompanies this distribution. The full text of the license may be found at
	9	# http://opensource.org/licenses/bsd-license.php
	10	#
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	13	#
	14	#------------------------------------------------------------------------------
	15
1bfda055	16	#include <AsmMacroIoLib.h>
1bfda055	17
2ef2b01e A	18	.text
2ef2b01e A	19	.align 2
0c0e7ef4	20	GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
0c0e7ef4	21	GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
1bfda055	22	GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
	23	GCC_ASM_EXPORT(ArmCleanDataCache)
	24	GCC_ASM_EXPORT(ArmInvalidateDataCache)
	25	GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
	26	GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
	27	GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
	28	GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
	29	GCC_ASM_EXPORT(ArmEnableMmu)
	30	GCC_ASM_EXPORT(ArmDisableMmu)
	31	GCC_ASM_EXPORT(ArmMmuEnabled)
	32	GCC_ASM_EXPORT(ArmEnableDataCache)
	33	GCC_ASM_EXPORT(ArmDisableDataCache)
	34	GCC_ASM_EXPORT(ArmEnableInstructionCache)
	35	GCC_ASM_EXPORT(ArmDisableInstructionCache)
	36	GCC_ASM_EXPORT(ArmEnableBranchPrediction)
	37	GCC_ASM_EXPORT(ArmDisableBranchPrediction)
	38	GCC_ASM_EXPORT(ArmDataMemoryBarrier)
	39	GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
	40	GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
0c0e7ef4	41	GCC_ASM_EXPORT(ArmSetLowVectors)
	42	GCC_ASM_EXPORT(ArmSetHighVectors)
	43	GCC_ASM_EXPORT(ArmIsMpCore)
	44	GCC_ASM_EXPORT(ArmCallWFI)
	45	GCC_ASM_EXPORT(ArmReadMpidr)
	46	GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
	47	GCC_ASM_EXPORT(ArmEnableFiq)
	48	GCC_ASM_EXPORT(ArmDisableFiq)
	49	GCC_ASM_EXPORT(ArmEnableInterrupts)
	50	GCC_ASM_EXPORT(ArmDisableInterrupts)
	51	GCC_ASM_EXPORT (ArmEnableVFP)
026c3d34	52
0c0e7ef4	53	Arm11PartNumberMask: .word 0xFFF0
0c0e7ef4	54	Arm11PartNumber: .word 0xB020
2ef2b01e A	55
	56	.set DC_ON, (0x1<<2)
	57	.set IC_ON, (0x1<<12)
	58	.set XP_ON, (0x1<<23)
0c0e7ef4	59	.set CTRL_M_BIT, (1 << 0)
	60	.set CTRL_C_BIT, (1 << 2)
	61	.set CTRL_I_BIT, (1 << 12)
	62
	63	ASM_PFX(ArmDisableCachesAndMmu):
	64	mrc p15, 0, r0, c1, c0, 0 @ Get control register
	65	bic r0, r0, #CTRL_M_BIT @ Disable MMU
	66	bic r0, r0, #CTRL_C_BIT @ Disable D Cache
	67	bic r0, r0, #CTRL_I_BIT @ Disable I Cache
	68	mcr p15, 0, r0, c1, c0, 0 @ Write control register
	69	bx LR
	70
	71	ASM_PFX(ArmInvalidateInstructionAndDataTlb):
	72	mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
	73	bx lr
2ef2b01e A	74
	75	ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
	76	mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
	77	bx lr
	78
	79
	80	ASM_PFX(ArmCleanDataCacheEntryByMVA):
	81	mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
	82	bx lr
	83
	84
	85	ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
	86	mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
	87	bx lr
	88
	89
	90	ASM_PFX(ArmCleanDataCache):
	91	mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
	92	bx lr
	93
	94
	95	ASM_PFX(ArmCleanInvalidateDataCache):
	96	mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
	97	bx lr
	98
	99
	100	ASM_PFX(ArmInvalidateDataCache):
	101	mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
	102	bx lr
	103
	104
	105	ASM_PFX(ArmInvalidateInstructionCache):
	106	mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
	107	mov R0,#0
	108	mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
	109	bx lr
	110
	111	ASM_PFX(ArmEnableMmu):
	112	mrc p15,0,R0,c1,c0,0
	113	orr R0,R0,#1
	114	mcr p15,0,R0,c1,c0,0
	115	bx LR
	116
c2b5ca8b A	117	ASM_PFX(ArmMmuEnabled):
	118	mrc p15,0,R0,c1,c0,0
	119	and R0,R0,#1
	120	bx LR
	121
2ef2b01e A	122	ASM_PFX(ArmDisableMmu):
	123	mrc p15,0,R0,c1,c0,0
	124	bic R0,R0,#1
	125	mcr p15,0,R0,c1,c0,0
	126	mov R0,#0
	127	mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
	128	mov R0,#0
	129	mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
	130	bx LR
	131
	132	ASM_PFX(ArmEnableDataCache):
1bfda055	133	LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
2ef2b01e A	134	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	135	orr R0,R0,R1 @Set C bit
	136	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
	137	bx LR
	138
	139	ASM_PFX(ArmDisableDataCache):
1bfda055	140	LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
2ef2b01e A	141	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	142	bic R0,R0,R1 @Clear C bit
	143	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
	144	bx LR
	145
	146	ASM_PFX(ArmEnableInstructionCache):
	147	ldr R1,=IC_ON
	148	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	149	orr R0,R0,R1 @Set I bit
	150	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
	151	bx LR
	152
	153	ASM_PFX(ArmDisableInstructionCache):
	154	ldr R1,=IC_ON
	155	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	156	bic R0,R0,R1 @Clear I bit.
	157	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
	158	bx LR
	159
	160	ASM_PFX(ArmEnableBranchPrediction):
	161	mrc p15, 0, r0, c1, c0, 0
	162	orr r0, r0, #0x00000800
	163	mcr p15, 0, r0, c1, c0, 0
	164	bx LR
	165
	166	ASM_PFX(ArmDisableBranchPrediction):
	167	mrc p15, 0, r0, c1, c0, 0
	168	bic r0, r0, #0x00000800
	169	mcr p15, 0, r0, c1, c0, 0
	170	bx LR
	171
026c3d34	172	ASM_PFX(ArmDataMemoryBarrier):
	173	mov R0, #0
	174	mcr P15, #0, R0, C7, C10, #5
	175	bx LR
	176
	177	ASM_PFX(ArmDataSyncronizationBarrier):
	178	mov R0, #0
	179	mcr P15, #0, R0, C7, C10, #4
	180	bx LR
	181
	182	ASM_PFX(ArmInstructionSynchronizationBarrier):
	183	mov R0, #0
	184	mcr P15, #0, R0, C7, C5, #4
	185	bx LR
0c0e7ef4	186
	187	ASM_PFX(ArmSetLowVectors):
	188	mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
	189	bic r0, r0, #0x00002000 @ clear V bit
	190	mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
	191	bx LR
	192
	193	ASM_PFX(ArmSetHighVectors):
	194	mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
	195	orr r0, r0, #0x00002000 @ clear V bit
	196	mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
	197	bx LR
	198
	199	ASM_PFX(ArmIsMpCore):
	200	push { r1 }
	201	mrc p15, 0, r0, c0, c0, 0
	202	# Extract Part Number to check it is an ARM11MP core (0xB02)
	203	LoadConstantToReg (Arm11PartNumberMask, r1)
	204	and r0, r0, r1
	205	LoadConstantToReg (Arm11PartNumber, r1)
	206	cmp r0, r1
	207	movne r0, #0
	208	pop { r1 }
	209	bx lr
	210
	211	ASM_PFX(ArmCallWFI):
	212	wfi
	213	bx lr
	214
	215	ASM_PFX(ArmReadMpidr):
	216	mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
	217	bx lr
	218
	219	ASM_PFX(ArmEnableFiq):
	220	mrs R0,CPSR
	221	bic R0,R0,#0x40 @Enable FIQ interrupts
	222	msr CPSR_c,R0
	223	bx LR
	224
	225	ASM_PFX(ArmDisableFiq):
	226	mrs R0,CPSR
	227	orr R1,R0,#0x40 @Disable FIQ interrupts
	228	msr CPSR_c,R1
	229	tst R0,#0x80
	230	moveq R0,#1
	231	movne R0,#0
	232	bx LR
	233
	234	ASM_PFX(ArmEnableInterrupts):
	235	mrs R0,CPSR
	236	bic R0,R0,#0x80 @Enable IRQ interrupts
	237	msr CPSR_c,R0
	238	bx LR
	239
	240	ASM_PFX(ArmDisableInterrupts):
	241	mrs R0,CPSR
	242	orr R1,R0,#0x80 @Disable IRQ interrupts
	243	msr CPSR_c,R1
	244	tst R0,#0x80
	245	moveq R0,#1
	246	movne R0,#0
	247	bx LR
	248
	249	ASM_PFX(ArmEnableVFP):
250	# Read CPACR (Coprocessor Access Control Register)
251	mrc p15, 0, r0, c1, c0, 2
252	# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
253	orr r0, r0, #0x00f00000
254	# Write back CPACR (Coprocessor Access Control Register)
255	mcr p15, 0, r0, c1, c0, 2
256	# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
257	mov r0, #0x40000000
258	#TODO: Fixme - need compilation flag
259	#fmxr FPEXC, r0
260	bx lr
026c3d34	261
2ef2b01e	262	ASM_FUNCTION_REMOVE_IF_UNREFERENCED