[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmCleanInvalidateDataCache
    EXPORT  ArmCleanDataCache
    EXPORT  ArmInvalidateDataCache
    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction


DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )
XP_ON       EQU     ( 0x1:SHL:23 )


    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  bx      lr


ArmCleanDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  bx      lr


ArmCleanInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  bx      lr


ArmCleanDataCache
  mcr     p15, 0, r0, c7, c10, 0  ; clean entire data cache
  bx      lr


ArmCleanInvalidateDataCache
  mcr     p15, 0, r0, c7, c14, 0  ; clean and invalidate entire data cache
  bx      lr


ArmInvalidateDataCache
  mcr     p15, 0, r0, c7, c6, 0  ; invalidate entire data cache
  bx      lr


ArmInvalidateInstructionCache
  mcr     p15, 0, r0, c7, c5, 0  ;invalidate entire instruction cache
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4       ;Flush Prefetch buffer
  bx      lr

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ArmDisableMmu
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4      ;Flush Prefetch buffer
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  ORR     R0,R0,R1             ;Set I bit
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR

ArmEnableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

ArmDisableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmCleanInvalidateDataCache
	16	EXPORT ArmCleanDataCache
	17	EXPORT ArmInvalidateDataCache
	18	EXPORT ArmInvalidateInstructionCache
	19	EXPORT ArmInvalidateDataCacheEntryByMVA
	20	EXPORT ArmCleanDataCacheEntryByMVA
	21	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	22	EXPORT ArmEnableMmu
	23	EXPORT ArmDisableMmu
	24	EXPORT ArmEnableDataCache
	25	EXPORT ArmDisableDataCache
	26	EXPORT ArmEnableInstructionCache
	27	EXPORT ArmDisableInstructionCache
	28	EXPORT ArmEnableBranchPrediction
	29	EXPORT ArmDisableBranchPrediction
	30
	31
	32	DC_ON EQU ( 0x1:SHL:2 )
	33	IC_ON EQU ( 0x1:SHL:12 )
	34	XP_ON EQU ( 0x1:SHL:23 )
	35
	36
	37	AREA ArmCacheLib, CODE, READONLY
	38	PRESERVE8
	39
	40
	41	ArmInvalidateDataCacheEntryByMVA
	42	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	43	bx lr
	44
	45
	46	ArmCleanDataCacheEntryByMVA
	47	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
	48	bx lr
	49
	50
	51	ArmCleanInvalidateDataCacheEntryByMVA
	52	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	53	bx lr
	54
	55
	56	ArmCleanDataCache
	57	mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
	58	bx lr
	59
	60
	61	ArmCleanInvalidateDataCache
	62	mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
	63	bx lr
	64
65
66	ArmInvalidateDataCache
67	mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
68	bx lr
69
70
71	ArmInvalidateInstructionCache
72	mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
73	mov R0,#0
74	mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
75	bx lr
76
77	ArmEnableMmu
78	mrc p15,0,R0,c1,c0,0
79	orr R0,R0,#1
80	mcr p15,0,R0,c1,c0,0
81	bx LR
82
83	ArmDisableMmu
84	mrc p15,0,R0,c1,c0,0
85	bic R0,R0,#1
86	mcr p15,0,R0,c1,c0,0
87	mov R0,#0
88	mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
89	mov R0,#0
90	mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
91	bx LR
92
93	ArmEnableDataCache
94	LDR R1,=DC_ON
95	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
96	ORR R0,R0,R1 ;Set C bit
97	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
98	BX LR
99
100	ArmDisableDataCache
101	LDR R1,=DC_ON
102	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
103	BIC R0,R0,R1 ;Clear C bit
104	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
105	BX LR
106
107	ArmEnableInstructionCache
108	LDR R1,=IC_ON
109	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
110	ORR R0,R0,R1 ;Set I bit
111	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
112	BX LR
113
114	ArmDisableInstructionCache
115	LDR R1,=IC_ON
116	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
117	BIC R0,R0,R1 ;Clear I bit.
118	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
119	BX LR
120
121	ArmEnableBranchPrediction
122	mrc p15, 0, r0, c1, c0, 0
123	orr r0, r0, #0x00000800
124	mcr p15, 0, r0, c1, c0, 0
125	bx LR
126
127	ArmDisableBranchPrediction
128	mrc p15, 0, r0, c1, c0, 0
129	bic r0, r0, #0x00000800
130	mcr p15, 0, r0, c1, c0, 0
131	bx LR
132
133	END