[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmLibPrivate.h

/** @file\r
  ArmLibPrivate.h\r
\r
  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef ARM_LIB_PRIVATE_H_\r
#define ARM_LIB_PRIVATE_H_\r
\r
#define CACHE_SIZE_4_KB             (3UL)\r
#define CACHE_SIZE_8_KB             (4UL)\r
#define CACHE_SIZE_16_KB            (5UL)\r
#define CACHE_SIZE_32_KB            (6UL)\r
#define CACHE_SIZE_64_KB            (7UL)\r
#define CACHE_SIZE_128_KB           (8UL)\r
\r
#define CACHE_ASSOCIATIVITY_DIRECT  (0UL)\r
#define CACHE_ASSOCIATIVITY_4_WAY   (2UL)\r
#define CACHE_ASSOCIATIVITY_8_WAY   (3UL)\r
\r
#define CACHE_PRESENT               (0UL)\r
#define CACHE_NOT_PRESENT           (1UL)\r
\r
#define CACHE_LINE_LENGTH_32_BYTES  (2UL)\r
\r
#define SIZE_FIELD_TO_CACHE_SIZE(x)           (((x) >> 6) & 0x0F)\r
#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x)  (((x) >> 3) & 0x07)\r
#define SIZE_FIELD_TO_CACHE_PRESENCE(x)       (((x) >> 2) & 0x01)\r
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x)    (((x) >> 0) & 0x03)\r
\r
#define DATA_CACHE_SIZE_FIELD(x)              (((x) >> 12) & 0x0FFF)\r
#define INSTRUCTION_CACHE_SIZE_FIELD(x)       (((x) >>  0) & 0x0FFF)\r
\r
#define DATA_CACHE_SIZE(x)                    (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
#define DATA_CACHE_ASSOCIATIVITY(x)           (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
#define DATA_CACHE_PRESENT(x)                 (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
#define DATA_CACHE_LINE_LENGTH(x)             (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
\r
#define INSTRUCTION_CACHE_SIZE(x)             (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
#define INSTRUCTION_CACHE_ASSOCIATIVITY(x)    (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
#define INSTRUCTION_CACHE_PRESENT(x)          (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
#define INSTRUCTION_CACHE_LINE_LENGTH(x)      (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
\r
#define CACHE_TYPE(x)                         (((x) >> 25) & 0x0F)\r
#define CACHE_TYPE_WRITE_BACK                 (0x0EUL)\r
\r
#define CACHE_ARCHITECTURE(x)                 (((x) >> 24) & 0x01)\r
#define CACHE_ARCHITECTURE_UNIFIED            (0UL)\r
#define CACHE_ARCHITECTURE_SEPARATE           (1UL)\r
\r
\r
/// Defines the structure of the CSSELR (Cache Size Selection) register\r
typedef union {\r
  struct {\r
    UINT32    InD       :1;  ///< Instruction not Data bit\r
    UINT32    Level     :3;  ///< Cache level (zero based)\r
    UINT32    TnD       :1;  ///< Allocation not Data bit\r
    UINT32    Reserved  :27; ///< Reserved, RES0\r
  } Bits; ///< Bitfield definition of the register\r
  UINT32 Data; ///< The entire 32-bit value\r
} CSSELR_DATA;\r
\r
/// The cache type values for the InD field of the CSSELR register\r
typedef enum\r
{\r
  /// Select the data or unified cache\r
  CsselrCacheTypeDataOrUnified = 0,\r
  /// Select the instruction cache\r
  CsselrCacheTypeInstruction,\r
  CsselrCacheTypeMax\r
} CSSELR_CACHE_TYPE;\r
\r
/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
typedef union {\r
  struct {\r
    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
    UINT64    Associativity      :10; ///< Associativity - 1\r
    UINT64    NumSets            :15; ///< Number of sets in the cache -1\r
    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN\r
    UINT64    Reserved           :32; ///< Reserved, RES0\r
  } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
  struct {\r
    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
    UINT64    Associativity      :21; ///< Associativity - 1\r
    UINT64    Reserved1          :8;  ///< Reserved, RES0\r
    UINT64    NumSets            :24; ///< Number of sets in the cache -1\r
    UINT64    Reserved2          :8;  ///< Reserved, RES0\r
  } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
  struct {\r
    UINT64    LineSize           : 3;\r
    UINT64    Associativity      : 21;\r
    UINT64    Reserved           : 8;\r
    UINT64    Unallocated        : 32;\r
  } BitsCcidxAA32;\r
  UINT64 Data; ///< The entire 64-bit value\r
} CCSIDR_DATA;\r
\r
/// Defines the structure of the AARCH32 CCSIDR2 register.\r
typedef union {\r
  struct {\r
    UINT32 NumSets               :24; ///< Number of sets in the cache - 1\r
    UINT32 Reserved              :8;  ///< Reserved, RES0\r
  } Bits; ///< Bitfield definition of the register\r
  UINT32 Data; ///< The entire 32-bit value\r
} CCSIDR2_DATA;\r
\r
/** Defines the structure of the CLIDR (Cache Level ID) register.\r
 *\r
 * The lower 32 bits are the same for both AARCH32 and AARCH64\r
 * so we can use the same structure for both.\r
**/\r
typedef union {\r
  struct {\r
    UINT32    Ctype1   : 3; ///< Level 1 cache type\r
    UINT32    Ctype2   : 3; ///< Level 2 cache type\r
    UINT32    Ctype3   : 3; ///< Level 3 cache type\r
    UINT32    Ctype4   : 3; ///< Level 4 cache type\r
    UINT32    Ctype5   : 3; ///< Level 5 cache type\r
    UINT32    Ctype6   : 3; ///< Level 6 cache type\r
    UINT32    Ctype7   : 3; ///< Level 7 cache type\r
    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable\r
    UINT32    LoC      : 3; ///< Level of Coherency\r
    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor\r
    UINT32    Icb      : 3; ///< Inner Cache Boundary\r
  } Bits; ///< Bitfield definition of the register\r
  UINT32 Data; ///< The entire 32-bit value\r
} CLIDR_DATA;\r
\r
/// The cache types reported in the CLIDR register.\r
typedef enum {\r
  /// No cache is present\r
  ClidrCacheTypeNone = 0,\r
  /// There is only an instruction cache\r
  ClidrCacheTypeInstructionOnly,\r
  /// There is only a data cache\r
  ClidrCacheTypeDataOnly,\r
  /// There are separate data and instruction caches\r
  ClidrCacheTypeSeparate,\r
  /// There is a unified cache\r
  ClidrCacheTypeUnified,\r
  ClidrCacheTypeMax\r
} CLIDR_CACHE_TYPE;\r
\r
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
\r
VOID\r
CPSRMaskInsert (\r
  IN  UINT32  Mask,\r
  IN  UINT32  Value\r
  );\r
\r
UINT32\r
CPSRRead (\r
  VOID\r
  );\r
\r
/** Reads the CCSIDR register for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value.\r
\r
  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
          Returns the contents of the CCSIDR register in AARCH32 mode.\r
**/\r
UINTN\r
ReadCCSIDR (\r
  IN UINT32 CSSELR\r
  );\r
\r
/** Reads the CCSIDR2 for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value\r
\r
  @return The contents of the CCSIDR2 register for the specified cache.\r
**/\r
UINT32\r
ReadCCSIDR2 (\r
  IN UINT32 CSSELR\r
  );\r
\r
UINT32\r
ReadCLIDR (\r
  VOID\r
  );\r
\r
#endif // ARM_LIB_PRIVATE_H_\r
Commit	Line	Data
2ef2b01e	1	/** @file\r
cd9fb745	2	ArmLibPrivate.h\r
2ef2b01e	3	\r
cd9fb745	4	Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
d6ebcab7	5	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
2ef2b01e	6	\r
4059386c	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
2ef2b01e A	8	\r
	9	**/\r
	10	\r
cc15a619 PG	11	#ifndef ARM_LIB_PRIVATE_H_\r
cc15a619 PG	12	#define ARM_LIB_PRIVATE_H_\r
2ef2b01e A	13	\r
	14	#define CACHE_SIZE_4_KB (3UL)\r
	15	#define CACHE_SIZE_8_KB (4UL)\r
	16	#define CACHE_SIZE_16_KB (5UL)\r
	17	#define CACHE_SIZE_32_KB (6UL)\r
	18	#define CACHE_SIZE_64_KB (7UL)\r
	19	#define CACHE_SIZE_128_KB (8UL)\r
	20	\r
	21	#define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r
	22	#define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r
	23	#define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r
	24	\r
	25	#define CACHE_PRESENT (0UL)\r
	26	#define CACHE_NOT_PRESENT (1UL)\r
	27	\r
	28	#define CACHE_LINE_LENGTH_32_BYTES (2UL)\r
	29	\r
	30	#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)\r
	31	#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)\r
	32	#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r
	33	#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r
	34	\r
	35	#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r
	36	#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r
	37	\r
	38	#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
	39	#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
	40	#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
	41	#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
	42	\r
	43	#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
	44	#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
	45	#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
	46	#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
	47	\r
	48	#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r
	49	#define CACHE_TYPE_WRITE_BACK (0x0EUL)\r
	50	\r
	51	#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r
	52	#define CACHE_ARCHITECTURE_UNIFIED (0UL)\r
	53	#define CACHE_ARCHITECTURE_SEPARATE (1UL)\r
	54	\r
cd9fb745 RC	55	\r
	56	/// Defines the structure of the CSSELR (Cache Size Selection) register\r
	57	typedef union {\r
	58	struct {\r
	59	UINT32 InD :1; ///< Instruction not Data bit\r
	60	UINT32 Level :3; ///< Cache level (zero based)\r
	61	UINT32 TnD :1; ///< Allocation not Data bit\r
	62	UINT32 Reserved :27; ///< Reserved, RES0\r
	63	} Bits; ///< Bitfield definition of the register\r
	64	UINT32 Data; ///< The entire 32-bit value\r
	65	} CSSELR_DATA;\r
	66	\r
	67	/// The cache type values for the InD field of the CSSELR register\r
	68	typedef enum\r
	69	{\r
	70	/// Select the data or unified cache\r
	71	CsselrCacheTypeDataOrUnified = 0,\r
	72	/// Select the instruction cache\r
	73	CsselrCacheTypeInstruction,\r
	74	CsselrCacheTypeMax\r
	75	} CSSELR_CACHE_TYPE;\r
	76	\r
	77	/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
	78	typedef union {\r
	79	struct {\r
	80	UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
	81	UINT64 Associativity :10; ///< Associativity - 1\r
	82	UINT64 NumSets :15; ///< Number of sets in the cache -1\r
	83	UINT64 Unknown :4; ///< Reserved, UNKNOWN\r
	84	UINT64 Reserved :32; ///< Reserved, RES0\r
	85	} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
	86	struct {\r
	87	UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
	88	UINT64 Associativity :21; ///< Associativity - 1\r
	89	UINT64 Reserved1 :8; ///< Reserved, RES0\r
	90	UINT64 NumSets :24; ///< Number of sets in the cache -1\r
	91	UINT64 Reserved2 :8; ///< Reserved, RES0\r
	92	} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
	93	struct {\r
	94	UINT64 LineSize : 3;\r
	95	UINT64 Associativity : 21;\r
	96	UINT64 Reserved : 8;\r
	97	UINT64 Unallocated : 32;\r
	98	} BitsCcidxAA32;\r
	99	UINT64 Data; ///< The entire 64-bit value\r
	100	} CCSIDR_DATA;\r
	101	\r
	102	/// Defines the structure of the AARCH32 CCSIDR2 register.\r
	103	typedef union {\r
	104	struct {\r
	105	UINT32 NumSets :24; ///< Number of sets in the cache - 1\r
	106	UINT32 Reserved :8; ///< Reserved, RES0\r
	107	} Bits; ///< Bitfield definition of the register\r
	108	UINT32 Data; ///< The entire 32-bit value\r
	109	} CCSIDR2_DATA;\r
	110	\r
	111	/** Defines the structure of the CLIDR (Cache Level ID) register.\r
	112	*\r
	113	* The lower 32 bits are the same for both AARCH32 and AARCH64\r
	114	* so we can use the same structure for both.\r
	115	**/\r
	116	typedef union {\r
	117	struct {\r
	118	UINT32 Ctype1 : 3; ///< Level 1 cache type\r
119	UINT32 Ctype2 : 3; ///< Level 2 cache type\r
120	UINT32 Ctype3 : 3; ///< Level 3 cache type\r
121	UINT32 Ctype4 : 3; ///< Level 4 cache type\r
122	UINT32 Ctype5 : 3; ///< Level 5 cache type\r
123	UINT32 Ctype6 : 3; ///< Level 6 cache type\r
124	UINT32 Ctype7 : 3; ///< Level 7 cache type\r
125	UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
126	UINT32 LoC : 3; ///< Level of Coherency\r
127	UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
128	UINT32 Icb : 3; ///< Inner Cache Boundary\r
129	} Bits; ///< Bitfield definition of the register\r
130	UINT32 Data; ///< The entire 32-bit value\r
131	} CLIDR_DATA;\r
132	\r
133	/// The cache types reported in the CLIDR register.\r
134	typedef enum {\r
135	/// No cache is present\r
136	ClidrCacheTypeNone = 0,\r
137	/// There is only an instruction cache\r
138	ClidrCacheTypeInstructionOnly,\r
139	/// There is only a data cache\r
140	ClidrCacheTypeDataOnly,\r
141	/// There are separate data and instruction caches\r
142	ClidrCacheTypeSeparate,\r
143	/// There is a unified cache\r
144	ClidrCacheTypeUnified,\r
145	ClidrCacheTypeMax\r
146	} CLIDR_CACHE_TYPE;\r
147	\r
148	#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
149	\r
2ef2b01e A	150	VOID\r
	151	CPSRMaskInsert (\r
	152	IN UINT32 Mask,\r
	153	IN UINT32 Value\r
	154	);\r
	155	\r
	156	UINT32\r
	157	CPSRRead (\r
	158	VOID\r
	159	);\r
	160	\r
93ff7a4e RC	161	/** Reads the CCSIDR register for the specified cache.\r
	162	\r
	163	@param CSSELR The CSSELR cache selection register value.\r
	164	\r
	165	@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
	166	Returns the contents of the CCSIDR register in AARCH32 mode.\r
	167	**/\r
	168	UINTN\r
98bc0c8c	169	ReadCCSIDR (\r
98bc0c8c	170	IN UINT32 CSSELR\r
3402aac7 RC	171	);\r
3402aac7 RC	172	\r
84a6db75 RC	173	/** Reads the CCSIDR2 for the specified cache.\r
	174	\r
	175	@param CSSELR The CSSELR cache selection register value\r
	176	\r
	177	@return The contents of the CCSIDR2 register for the specified cache.\r
	178	**/\r
	179	UINT32\r
	180	ReadCCSIDR2 (\r
	181	IN UINT32 CSSELR\r
	182	);\r
	183	\r
98bc0c8c	184	UINT32\r
	185	ReadCLIDR (\r
	186	VOID\r
	187	);\r
98bc0c8c	188	\r
cc15a619	189	#endif // ARM_LIB_PRIVATE_H_\r