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1a27eb48 | 1 | //------------------------------------------------------------------------------ |
2 | // | |
d6ebcab7 | 3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> |
1a27eb48 | 4 | // |
d6ebcab7 | 5 | // This program and the accompanying materials |
1a27eb48 | 6 | // are licensed and made available under the terms and conditions of the BSD License |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | ||
16 | EXPORT Cp15IdCode | |
17 | EXPORT Cp15CacheInfo | |
18 | EXPORT ArmEnableInterrupts | |
19 | EXPORT ArmDisableInterrupts | |
20 | EXPORT ArmGetInterruptState | |
0416278c | 21 | EXPORT ArmEnableFiq |
22 | EXPORT ArmDisableFiq | |
23 | EXPORT ArmGetFiqState | |
1a27eb48 | 24 | EXPORT ArmInvalidateTlb |
25 | EXPORT ArmSetTranslationTableBaseAddress | |
26 | EXPORT ArmGetTranslationTableBaseAddress | |
27 | EXPORT ArmSetDomainAccessControl | |
bb02cb80 | 28 | EXPORT ArmUpdateTranslationTableEntry |
1a27eb48 | 29 | EXPORT CPSRMaskInsert |
30 | EXPORT CPSRRead | |
98bc0c8c | 31 | EXPORT ReadCCSIDR |
37b91c49 | 32 | EXPORT ReadCLIDR |
33 | ||
1a27eb48 | 34 | AREA ArmLibSupport, CODE, READONLY |
35 | ||
bb02cb80 | 36 | |
37 | //------------------------------------------------------------------------------ | |
38 | ||
1a27eb48 | 39 | Cp15IdCode |
1a27eb48 | 40 | mrc p15,0,R0,c0,c0,0 |
1a27eb48 | 41 | bx LR |
42 | ||
43 | Cp15CacheInfo | |
1a27eb48 | 44 | mrc p15,0,R0,c0,c0,1 |
1a27eb48 | 45 | bx LR |
46 | ||
47 | ArmEnableInterrupts | |
bb02cb80 | 48 | cpsie i |
1a27eb48 | 49 | bx LR |
50 | ||
51 | ArmDisableInterrupts | |
bb02cb80 | 52 | cpsid i |
1a27eb48 | 53 | bx LR |
54 | ||
55 | ArmGetInterruptState | |
1a27eb48 | 56 | mrs R0,CPSR |
57 | tst R0,#0x80 ;Check if IRQ is enabled. | |
58 | moveq R0,#1 | |
59 | movne R0,#0 | |
1a27eb48 | 60 | bx LR |
bb02cb80 | 61 | |
0416278c | 62 | ArmEnableFiq |
bb02cb80 | 63 | cpsie f |
0416278c | 64 | bx LR |
65 | ||
66 | ArmDisableFiq | |
bb02cb80 | 67 | cpsid f |
0416278c | 68 | bx LR |
69 | ||
70 | ArmGetFiqState | |
71 | mrs R0,CPSR | |
bb02cb80 | 72 | tst R0,#0x40 ;Check if FIQ is enabled. |
0416278c | 73 | moveq R0,#1 |
74 | movne R0,#0 | |
75 | bx LR | |
1a27eb48 | 76 | |
77 | ArmInvalidateTlb | |
1a27eb48 | 78 | mov r0,#0 |
79 | mcr p15,0,r0,c8,c7,0 | |
bb02cb80 | 80 | mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp |
81 | dsb | |
82 | isb | |
1a27eb48 | 83 | bx lr |
84 | ||
85 | ArmSetTranslationTableBaseAddress | |
1a27eb48 | 86 | mcr p15,0,r0,c2,c0,0 |
bb02cb80 | 87 | isb |
1a27eb48 | 88 | bx lr |
89 | ||
90 | ArmGetTranslationTableBaseAddress | |
1a27eb48 | 91 | mrc p15,0,r0,c2,c0,0 |
bb02cb80 | 92 | isb |
1a27eb48 | 93 | bx lr |
94 | ||
bb02cb80 | 95 | |
1a27eb48 | 96 | ArmSetDomainAccessControl |
1a27eb48 | 97 | mcr p15,0,r0,c3,c0,0 |
bb02cb80 | 98 | isb |
99 | bx lr | |
100 | ||
101 | // | |
102 | //VOID | |
103 | //ArmUpdateTranslationTableEntry ( | |
104 | // IN VOID *TranslationTableEntry // R0 | |
105 | // IN VOID *MVA // R1 | |
106 | // ); | |
107 | ArmUpdateTranslationTableEntry | |
108 | mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA | |
109 | dsb | |
110 | mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA | |
111 | mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp | |
112 | dsb | |
113 | isb | |
1a27eb48 | 114 | bx lr |
115 | ||
116 | CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert | |
1a27eb48 | 117 | stmfd sp!, {r4-r12, lr} ; save all the banked registers |
118 | mov r3, sp ; copy the stack pointer into a non-banked register | |
119 | mrs r2, cpsr ; read the cpsr | |
120 | bic r2, r2, r0 ; clear mask in the cpsr | |
121 | and r1, r1, r0 ; clear bits outside the mask in the input | |
122 | orr r2, r2, r1 ; set field | |
123 | msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) | |
bb02cb80 | 124 | isb |
1a27eb48 | 125 | mov sp, r3 ; restore stack pointer |
126 | ldmfd sp!, {r4-r12, lr} ; restore registers | |
1a27eb48 | 127 | bx lr ; return (hopefully thumb-safe!) |
128 | ||
129 | CPSRRead | |
1a27eb48 | 130 | mrs r0, cpsr |
1a27eb48 | 131 | bx lr |
132 | ||
98bc0c8c | 133 | |
134 | // UINT32 | |
135 | // ReadCCSIDR ( | |
136 | // IN UINT32 CSSELR | |
137 | // ) | |
138 | ReadCCSIDR | |
bb02cb80 | 139 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) |
140 | isb | |
141 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) | |
142 | bx lr | |
98bc0c8c | 143 | |
144 | ||
145 | // UINT32 | |
146 | // ReadCLIDR ( | |
147 | // IN UINT32 CSSELR | |
148 | // ) | |
149 | ReadCLIDR | |
bb02cb80 | 150 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register |
151 | bx lr | |
152 | ||
153 | ||
154 | END | |
1a27eb48 | 155 | |
156 |