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3402aac7 | 1 | #------------------------------------------------------------------------------\r |
bd6b9799 | 2 | #\r |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
d6dc67ba | 4 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | #\r |
6 | # This program and the accompanying materials\r | |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <AsmMacroIoLib.h>\r | |
17 | \r | |
18 | .text\r | |
19 | .align 2\r | |
20 | \r | |
21 | GCC_ASM_EXPORT(ArmIsMpCore)\r | |
2ea66ed9 | 22 | GCC_ASM_EXPORT(ArmHasMpExtensions)\r |
bd6b9799 | 23 | GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)\r |
24 | GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)\r | |
25 | GCC_ASM_EXPORT(ArmEnableIrq)\r | |
26 | GCC_ASM_EXPORT(ArmDisableIrq)\r | |
27 | GCC_ASM_EXPORT(ArmEnableFiq)\r | |
28 | GCC_ASM_EXPORT(ArmDisableFiq)\r | |
29 | GCC_ASM_EXPORT(ArmEnableInterrupts)\r | |
30 | GCC_ASM_EXPORT(ArmDisableInterrupts)\r | |
31 | GCC_ASM_EXPORT(ReadCCSIDR)\r | |
32 | GCC_ASM_EXPORT(ReadCLIDR)\r | |
d6dc67ba OM |
33 | GCC_ASM_EXPORT(ArmReadNsacr)\r |
34 | GCC_ASM_EXPORT(ArmWriteNsacr)\r | |
bd6b9799 | 35 | \r |
36 | #------------------------------------------------------------------------------\r | |
37 | \r | |
38 | ASM_PFX(ArmIsMpCore):\r | |
39 | mrc p15,0,R0,c0,c0,5\r | |
40 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
41 | and R0, R0, #0xC0000000\r | |
5a539eb5 OM |
42 | // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r |
43 | cmp R0, #0x80000000\r | |
44 | moveq R0, #1\r | |
45 | movne R0, #0\r | |
bd6b9799 | 46 | bx LR\r |
47 | \r | |
48 | ASM_PFX(ArmEnableAsynchronousAbort):\r | |
49 | cpsie a\r | |
50 | isb\r | |
51 | bx LR\r | |
52 | \r | |
53 | ASM_PFX(ArmDisableAsynchronousAbort):\r | |
54 | cpsid a\r | |
55 | isb\r | |
56 | bx LR\r | |
57 | \r | |
58 | ASM_PFX(ArmEnableIrq):\r | |
59 | cpsie i\r | |
60 | isb\r | |
61 | bx LR\r | |
62 | \r | |
63 | ASM_PFX(ArmDisableIrq):\r | |
64 | cpsid i\r | |
65 | isb\r | |
66 | bx LR\r | |
67 | \r | |
68 | ASM_PFX(ArmEnableFiq):\r | |
69 | cpsie f\r | |
70 | isb\r | |
71 | bx LR\r | |
72 | \r | |
73 | ASM_PFX(ArmDisableFiq):\r | |
74 | cpsid f\r | |
75 | isb\r | |
76 | bx LR\r | |
77 | \r | |
78 | ASM_PFX(ArmEnableInterrupts):\r | |
79 | cpsie if\r | |
80 | isb\r | |
81 | bx LR\r | |
82 | \r | |
83 | ASM_PFX(ArmDisableInterrupts):\r | |
84 | cpsid if\r | |
85 | isb\r | |
86 | bx LR\r | |
3402aac7 RC |
87 | \r |
88 | // UINT32\r | |
bd6b9799 | 89 | // ReadCCSIDR (\r |
90 | // IN UINT32 CSSELR\r | |
3402aac7 | 91 | // )\r |
bd6b9799 | 92 | ASM_PFX(ReadCCSIDR):\r |
93 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r | |
94 | isb\r | |
95 | mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r | |
96 | bx lr\r | |
3402aac7 RC |
97 | \r |
98 | // UINT32\r | |
bd6b9799 | 99 | // ReadCLIDR (\r |
100 | // IN UINT32 CSSELR\r | |
3402aac7 | 101 | // )\r |
bd6b9799 | 102 | ASM_PFX(ReadCLIDR):\r |
103 | mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r | |
104 | bx lr\r | |
105 | \r | |
d6dc67ba OM |
106 | ASM_PFX(ArmReadNsacr):\r |
107 | mrc p15, 0, r0, c1, c1, 2\r | |
108 | bx lr\r | |
109 | \r | |
110 | ASM_PFX(ArmWriteNsacr):\r | |
111 | mcr p15, 0, r0, c1, c1, 2\r | |
112 | bx lr\r | |
113 | \r | |
bd6b9799 | 114 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |