| bd6b9799 |
1 | //------------------------------------------------------------------------------ \r |
| 2 | //\r |
| 3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r |
| 4 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 5 | //\r |
| 6 | // This program and the accompanying materials\r |
| 7 | // are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | // which accompanies this distribution. The full text of the license may be found at\r |
| 9 | // http://opensource.org/licenses/bsd-license.php\r |
| 10 | //\r |
| 11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | //\r |
| 14 | //------------------------------------------------------------------------------\r |
| 15 | \r |
| 16 | \r |
| 17 | EXPORT ArmIsMpCore\r |
| 18 | EXPORT ArmEnableAsynchronousAbort\r |
| 19 | EXPORT ArmDisableAsynchronousAbort\r |
| 20 | EXPORT ArmEnableIrq\r |
| 21 | EXPORT ArmDisableIrq\r |
| 22 | EXPORT ArmEnableFiq\r |
| 23 | EXPORT ArmDisableFiq\r |
| 24 | EXPORT ArmEnableInterrupts\r |
| 25 | EXPORT ArmDisableInterrupts\r |
| 26 | EXPORT ReadCCSIDR\r |
| 27 | EXPORT ReadCLIDR\r |
| 28 | \r |
| 29 | AREA ArmLibSupportV7, CODE, READONLY\r |
| 30 | \r |
| 31 | \r |
| 32 | //------------------------------------------------------------------------------\r |
| 33 | \r |
| 34 | ArmIsMpCore\r |
| 35 | mrc p15,0,R0,c0,c0,5\r |
| 36 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r |
| 37 | and R0, R0, #0xC0000000\r |
| 38 | // if bit30 == 0 then the processor is part of a multiprocessor system)\r |
| 39 | and R0, R0, #0x80000000\r |
| 40 | bx LR\r |
| 41 | \r |
| 42 | ArmEnableAsynchronousAbort\r |
| 43 | cpsie a\r |
| 44 | isb\r |
| 45 | bx LR\r |
| 46 | \r |
| 47 | ArmDisableAsynchronousAbort\r |
| 48 | cpsid a\r |
| 49 | isb\r |
| 50 | bx LR\r |
| 51 | \r |
| 52 | ArmEnableIrq\r |
| 53 | cpsie i\r |
| 54 | isb\r |
| 55 | bx LR\r |
| 56 | \r |
| 57 | ArmDisableIrq\r |
| 58 | cpsid i\r |
| 59 | isb\r |
| 60 | bx LR\r |
| 61 | \r |
| 62 | ArmEnableFiq\r |
| 63 | cpsie f\r |
| 64 | isb\r |
| 65 | bx LR\r |
| 66 | \r |
| 67 | ArmDisableFiq\r |
| 68 | cpsid f\r |
| 69 | isb\r |
| 70 | bx LR\r |
| 71 | \r |
| 72 | ArmEnableInterrupts\r |
| 73 | cpsie if\r |
| 74 | isb\r |
| 75 | bx LR\r |
| 76 | \r |
| 77 | ArmDisableInterrupts\r |
| 78 | cpsid if\r |
| 79 | isb\r |
| 80 | bx LR\r |
| 81 | \r |
| 82 | // UINT32 \r |
| 83 | // ReadCCSIDR (\r |
| 84 | // IN UINT32 CSSELR\r |
| 85 | // ) \r |
| 86 | ReadCCSIDR\r |
| 87 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r |
| 88 | isb\r |
| 89 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r |
| 90 | bx lr\r |
| 91 | \r |
| 92 | // UINT32 \r |
| 93 | // ReadCLIDR (\r |
| 94 | // IN UINT32 CSSELR\r |
| 95 | // ) \r |
| 96 | ReadCLIDR\r |
| 97 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r |
| 98 | bx lr\r |
| 99 | \r |
| 2575b726 |
100 | END\r |
projects / mirror_edk2.git / blame