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ArmPkg/ArmV7Lib: Add support for Invalid Instruction Cache to Point of Unification
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Lib.c
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1/** @file
2
d6ebcab7 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
2ef2b01e 4
d6ebcab7 5 This program and the accompanying materials
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6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
98bc0c8c 14#include <Uefi.h>
5dea9bd6 15#include <Chipset/ArmV7.h>
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16#include <Library/ArmLib.h>
17#include <Library/BaseLib.h>
1bfda055 18#include <Library/IoLib.h>
5dea9bd6 19#include "ArmV7Lib.h"
98bc0c8c 20#include "ArmLibPrivate.h"
2ef2b01e 21
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22ARM_CACHE_TYPE
23EFIAPI
24ArmCacheType (
25 VOID
26 )
27{
28 return ARM_CACHE_TYPE_WRITE_BACK;
29}
30
31ARM_CACHE_ARCHITECTURE
32EFIAPI
33ArmCacheArchitecture (
34 VOID
35 )
36{
98bc0c8c 37 UINT32 CLIDR = ReadCLIDR ();
38
1bfda055 39 return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
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40}
41
42BOOLEAN
43EFIAPI
44ArmDataCachePresent (
45 VOID
46 )
47{
98bc0c8c 48 UINT32 CLIDR = ReadCLIDR ();
49
50 if ((CLIDR & 0x2) == 0x2) {
51 // Instruction cache exists
52 return TRUE;
53 }
54 if ((CLIDR & 0x7) == 0x4) {
55 // Unified cache
56 return TRUE;
57 }
58
59 return FALSE;
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60}
61
62UINTN
63EFIAPI
64ArmDataCacheSize (
65 VOID
66 )
67{
98bc0c8c 68 UINT32 NumSets;
69 UINT32 Associativity;
70 UINT32 LineSize;
71 UINT32 CCSIDR = ReadCCSIDR (0);
72
1bfda055 73 LineSize = (1 << ((CCSIDR & 0x7) + 2));
98bc0c8c 74 Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
75 NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
76
77 // LineSize is in words (4 byte chunks)
78 return NumSets * Associativity * LineSize * 4;
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79}
80
81UINTN
82EFIAPI
83ArmDataCacheAssociativity (
84 VOID
85 )
86{
98bc0c8c 87 UINT32 CCSIDR = ReadCCSIDR (0);
88
89 return ((CCSIDR >> 3) & 0x3ff) + 1;
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90}
91
92UINTN
93ArmDataCacheSets (
94 VOID
95 )
96{
98bc0c8c 97 UINT32 CCSIDR = ReadCCSIDR (0);
98
99 return ((CCSIDR >> 13) & 0x7fff) + 1;
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100}
101
102UINTN
103EFIAPI
104ArmDataCacheLineLength (
105 VOID
106 )
107{
98bc0c8c 108 UINT32 CCSIDR = ReadCCSIDR (0) & 7;
109
110 // * 4 converts to bytes
111 return (1 << (CCSIDR + 2)) * 4;
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112}
113
114BOOLEAN
115EFIAPI
116ArmInstructionCachePresent (
117 VOID
118 )
119{
98bc0c8c 120 UINT32 CLIDR = ReadCLIDR ();
121
122 if ((CLIDR & 1) == 1) {
123 // Instruction cache exists
124 return TRUE;
125 }
126 if ((CLIDR & 0x7) == 0x4) {
127 // Unified cache
128 return TRUE;
129 }
130
131 return FALSE;
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132}
133
134UINTN
135EFIAPI
136ArmInstructionCacheSize (
137 VOID
138 )
139{
98bc0c8c 140 UINT32 NumSets;
141 UINT32 Associativity;
142 UINT32 LineSize;
143 UINT32 CCSIDR = ReadCCSIDR (1);
144
1bfda055 145 LineSize = (1 << ((CCSIDR & 0x7) + 2));
98bc0c8c 146 Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
147 NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
148
149 // LineSize is in words (4 byte chunks)
150 return NumSets * Associativity * LineSize * 4;
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151}
152
153UINTN
154EFIAPI
155ArmInstructionCacheAssociativity (
156 VOID
157 )
158{
98bc0c8c 159 UINT32 CCSIDR = ReadCCSIDR (1);
160
161 return ((CCSIDR >> 3) & 0x3ff) + 1;
162// return 4;
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163}
164
98bc0c8c 165UINTN
166EFIAPI
167ArmInstructionCacheSets (
168 VOID
169 )
170{
171 UINT32 CCSIDR = ReadCCSIDR (1);
172
173 return ((CCSIDR >> 13) & 0x7fff) + 1;
174}
175
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176UINTN
177EFIAPI
178ArmInstructionCacheLineLength (
179 VOID
180 )
181{
98bc0c8c 182 UINT32 CCSIDR = ReadCCSIDR (1) & 7;
183
184 // * 4 converts to bytes
185 return (1 << (CCSIDR + 2)) * 4;
186
187// return 64;
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188}
189
98bc0c8c 190
2ef2b01e 191VOID
5dea9bd6 192ArmV7DataCacheOperation (
193 IN ARM_V7_CACHE_OPERATION DataCacheOperation
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194 )
195{
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196 UINTN SavedInterruptState;
197
98bc0c8c 198 SavedInterruptState = ArmGetInterruptState ();
d60f6af4 199 ArmDisableInterrupts ();
1bfda055 200
98bc0c8c 201 ArmV7AllDataCachesOperation (DataCacheOperation);
2ef2b01e 202
98bc0c8c 203 ArmDrainWriteBuffer ();
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204
205 if (SavedInterruptState) {
98bc0c8c 206 ArmEnableInterrupts ();
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207 }
208}
209
d60f6af4 210
211VOID
212ArmV7PoUDataCacheOperation (
213 IN ARM_V7_CACHE_OPERATION DataCacheOperation
214 )
215{
216 UINTN SavedInterruptState;
217
218 SavedInterruptState = ArmGetInterruptState ();
219 ArmDisableInterrupts ();
220
221 ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
222
223 ArmDrainWriteBuffer ();
224
225 if (SavedInterruptState) {
226 ArmEnableInterrupts ();
227 }
228}
229
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230VOID
231EFIAPI
232ArmInvalidateDataCache (
233 VOID
234 )
235{
98bc0c8c 236 ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
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237}
238
239VOID
240EFIAPI
241ArmCleanInvalidateDataCache (
242 VOID
243 )
244{
98bc0c8c 245 ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
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246}
247
248VOID
249EFIAPI
250ArmCleanDataCache (
251 VOID
252 )
253{
98bc0c8c 254 ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
2ef2b01e 255}
1bfda055 256
d60f6af4 257VOID
258EFIAPI
259ArmCleanDataCacheToPoU (
260 VOID
261 )
262{
263 ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
264}