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1bfda055 | 1 | /** @file |
2 | * | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
4 | * | |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #include <Uefi.h> | |
16 | #include <Chipset/ArmV7.h> | |
17 | #include <Library/ArmLib.h> | |
18 | #include <Library/BaseLib.h> | |
19 | #include <Library/IoLib.h> | |
20 | #include "ArmV7Lib.h" | |
21 | #include "ArmLibPrivate.h" | |
22 | ||
23 | VOID | |
24 | EFIAPI | |
25 | ArmSetupSmpNonSecure ( | |
26 | IN UINTN CoreId | |
27 | ) | |
28 | { | |
29 | INTN scu_base; | |
30 | ||
31 | ArmSetAuxCrBit (A9_FEATURE_SMP); | |
32 | ||
33 | if (CoreId == 0) { | |
34 | scu_base = ArmGetScuBaseAddress(); | |
35 | ||
36 | // Allow NS access to SCU register | |
37 | MmioOr32(scu_base + SCU_SACR_OFFSET, 0xf); | |
38 | // Allow NS access to Private Peripherals | |
39 | MmioOr32(scu_base + SCU_SSACR_OFFSET, 0xfff); | |
40 | } | |
41 | } | |
42 | ||
43 | VOID | |
44 | EFIAPI | |
45 | ArmInvalidScu ( | |
46 | VOID | |
47 | ) | |
48 | { | |
49 | INTN scu_base; | |
50 | ||
51 | scu_base = ArmGetScuBaseAddress(); | |
52 | ||
53 | /* Invalidate all: write -1 to SCU Invalidate All register */ | |
54 | MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff); | |
55 | /* Enable SCU */ | |
56 | MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1); | |
57 | } |