[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
\r
    INCLUDE AsmMacroExport.inc\r
    PRESERVE8\r
\r
DC_ON           EQU     ( 0x1:SHL:2 )\r
IC_ON           EQU     ( 0x1:SHL:12 )\r
CTRL_M_BIT      EQU     (1 << 0)\r
CTRL_C_BIT      EQU     (1 << 2)\r
CTRL_B_BIT      EQU     (1 << 7)\r
CTRL_I_BIT      EQU     (1 << 12)\r
\r
\r
 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
  bx      lr\r
\r
\r
 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
  bx      lr\r
\r
\r
 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
  bx      lr\r
\r
\r
 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
  bx      lr\r
\r
\r
 RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
  bx      lr\r
\r
\r
 RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmEnableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDisableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
\r
  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB\r
  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
  mrc   p15, 0, r0, c1, c0, 0           ; Get control register\r
  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU\r
  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache\r
  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache\r
  mcr   p15, 0, r0, c1, c0, 0           ; Write control register\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmMmuEnabled\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  and     R0,R0,#1\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmEnableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDisableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmEnableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDisableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
  mrc     p15, 0, r0, c1, c0, 0\r
  orr     r0, r0, #0x00000400\r
  mcr     p15, 0, r0, c1, c0, 0\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmSetLowVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmSetHighVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00002000   ; Set V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
  stmfd SP!,{r4-r12, LR}\r
  mov   R1, R0                ; Save Function call in R1\r
  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)\r
  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)\r
  beq   Finished\r
  mov   R10, #0\r
\r
Loop1\r
  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
  and   R12, R12, #7            ; get those 3 bits alone\r
  cmp   R12, #2\r
  blt   Skip                    ; no cache or only instruction cache at this level\r
  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
  isb                           ; isb to sync the change to the CacheSizeID reg\r
  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
  and   R2, R12, #&7            ; extract the line length field\r
  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
  ldr   R4, =0x3FF\r
  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)\r
  clz   R5, R4                  ; R5 is the bit position of the way size increment\r
  ldr   R7, =0x00007FFF\r
  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
\r
Loop2\r
  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
\r
Loop3\r
  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
  orr   R0, R0, R7, LSL R2      ; factor in the index number\r
\r
  blx   R1\r
\r
  subs  R9, R9, #1              ; decrement the way number\r
  bge   Loop3\r
  subs  R7, R7, #1              ; decrement the index\r
  bge   Loop2\r
Skip\r
  add   R10, R10, #2            ; increment the cache number\r
  cmp   R3, R10\r
  bgt   Loop1\r
\r
Finished\r
  dsb\r
  ldmfd SP!, {r4-r12, lr}\r
  bx    LR\r
\r
 RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
  dmb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
  dsb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
  isb\r
  bx      LR\r
\r
 RVCT_ASM_EXPORT ArmReadVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mrc     p15, 0, r0, c12, c0, 0\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmWriteVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mcr     p15, 0, r0, c12, c0, 0\r
  // Ensure the SCTLR.V bit is clear\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmEnableVFP\r
  // Read CPACR (Coprocessor Access Control Register)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
  orr     r0, r0, #0x00f00000\r
  // Write back CPACR (Coprocessor Access Control Register)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  isb\r
  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
  mov     r0, #0x40000000\r
  mcr     p10,#0x7,r0,c8,c0,#0\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmCallWFI\r
  wfi\r
  bx      lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
 RVCT_ASM_EXPORT ArmReadCbar\r
  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmReadMpidr\r
  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmReadTpidrurw\r
  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmWriteTpidrurw\r
  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW\r
  bx      lr\r
\r
 RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1\r
  and    r0, r0, #0x000F0000\r
  bx     lr\r
\r
 RVCT_ASM_EXPORT ArmReadIdPfr1\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register\r
  bx     lr\r
\r
 RVCT_ASM_EXPORT ArmReadIdMmfr0\r
  mrc    p15, 0, r0, c0, c1, 4     ; Read ID_MMFR0 Register\r
  bx     lr\r
\r
 END\r
Commit	Line	Data
3402aac7	1	//------------------------------------------------------------------------------\r
bd6b9799	2	//\r
bd6b9799	3	// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
9401d6f4	4	// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
bd6b9799	5	//\r
	6	// This program and the accompanying materials\r
	7	// are licensed and made available under the terms and conditions of the BSD License\r
	8	// which accompanies this distribution. The full text of the license may be found at\r
	9	// http://opensource.org/licenses/bsd-license.php\r
	10	//\r
	11	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	//\r
	14	//------------------------------------------------------------------------------\r
	15	\r
efda1775 EC	16	\r
efda1775 EC	17	INCLUDE AsmMacroExport.inc\r
bd6b9799	18	PRESERVE8\r
	19	\r
	20	DC_ON EQU ( 0x1:SHL:2 )\r
	21	IC_ON EQU ( 0x1:SHL:12 )\r
	22	CTRL_M_BIT EQU (1 << 0)\r
	23	CTRL_C_BIT EQU (1 << 2)\r
	24	CTRL_B_BIT EQU (1 << 7)\r
	25	CTRL_I_BIT EQU (1 << 12)\r
	26	\r
	27	\r
efda1775	28	RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
3402aac7	29	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
bd6b9799	30	bx lr\r
bd6b9799	31	\r
efda1775	32	RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
3402aac7	33	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
bd6b9799	34	bx lr\r
	35	\r
	36	\r
efda1775	37	RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
bd6b9799	38	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
bd6b9799	39	bx lr\r
	40	\r
	41	\r
efda1775	42	RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
3402aac7	43	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
bd6b9799	44	bx lr\r
	45	\r
	46	\r
efda1775	47	RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
3402aac7	48	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
bd6b9799	49	bx lr\r
	50	\r
	51	\r
efda1775	52	RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
3402aac7	53	mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
bd6b9799	54	bx lr\r
	55	\r
	56	\r
efda1775	57	RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
bd6b9799	58	mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
	59	isb\r
	60	bx LR\r
	61	\r
efda1775	62	RVCT_ASM_EXPORT ArmEnableMmu\r
bd6b9799	63	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	64	orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
	65	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	66	dsb\r
	67	isb\r
	68	bx LR\r
	69	\r
efda1775	70	RVCT_ASM_EXPORT ArmDisableMmu\r
bd6b9799	71	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	72	bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
	73	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	74	\r
	75	mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
	76	mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
	77	dsb\r
	78	isb\r
	79	bx LR\r
	80	\r
efda1775	81	RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
bd6b9799	82	mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
	83	bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
	84	bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
	85	bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
	86	mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
	87	dsb\r
	88	isb\r
	89	bx LR\r
	90	\r
efda1775	91	RVCT_ASM_EXPORT ArmMmuEnabled\r
bd6b9799	92	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	93	and R0,R0,#1\r
	94	bx LR\r
	95	\r
efda1775	96	RVCT_ASM_EXPORT ArmEnableDataCache\r
bd6b9799	97	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	98	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	99	orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
	100	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	101	dsb\r
	102	isb\r
	103	bx LR\r
3402aac7	104	\r
efda1775	105	RVCT_ASM_EXPORT ArmDisableDataCache\r
bd6b9799	106	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	107	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	108	bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
	109	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	110	dsb\r
	111	isb\r
	112	bx LR\r
	113	\r
efda1775	114	RVCT_ASM_EXPORT ArmEnableInstructionCache\r
bd6b9799	115	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	116	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	117	orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
	118	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	119	dsb\r
	120	isb\r
	121	bx LR\r
3402aac7	122	\r
efda1775	123	RVCT_ASM_EXPORT ArmDisableInstructionCache\r
bd6b9799	124	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	125	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	126	BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
	127	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	128	isb\r
	129	bx LR\r
	130	\r
efda1775	131	RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
bd6b9799	132	mrc p15, 0, r0, c1, c0, 0\r
	133	orr r0, r0, #0x00000400\r
	134	mcr p15, 0, r0, c1, c0, 0\r
	135	isb\r
	136	bx LR\r
	137	\r
efda1775	138	RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
bd6b9799	139	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	140	orr r0, r0, #0x00000800 ;\r
	141	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	142	dsb\r
	143	isb\r
	144	bx LR\r
	145	\r
efda1775	146	RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
bd6b9799	147	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	148	bic r0, r0, #0x00000800 ;\r
	149	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	150	dsb\r
	151	isb\r
	152	bx LR\r
	153	\r
efda1775	154	RVCT_ASM_EXPORT ArmSetLowVectors\r
bd6b9799	155	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	156	bic r0, r0, #0x00002000 ; clear V bit\r
	157	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	158	isb\r
	159	bx LR\r
	160	\r
efda1775	161	RVCT_ASM_EXPORT ArmSetHighVectors\r
bd6b9799	162	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
c6ba1c12	163	orr r0, r0, #0x00002000 ; Set V bit\r
bd6b9799	164	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	165	isb\r
	166	bx LR\r
	167	\r
efda1775	168	RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
bd6b9799	169	stmfd SP!,{r4-r12, LR}\r
	170	mov R1, R0 ; Save Function call in R1\r
	171	mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
	172	ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
	173	mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
	174	beq Finished\r
	175	mov R10, #0\r
	176	\r
3402aac7	177	Loop1\r
bd6b9799	178	add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
	179	mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
	180	and R12, R12, #7 ; get those 3 bits alone\r
	181	cmp R12, #2\r
	182	blt Skip ; no cache or only instruction cache at this level\r
	183	mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
3402aac7	184	isb ; isb to sync the change to the CacheSizeID reg\r
bd6b9799	185	mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
	186	and R2, R12, #&7 ; extract the line length field\r
	187	add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
	188	ldr R4, =0x3FF\r
	189	ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
	190	clz R5, R4 ; R5 is the bit position of the way size increment\r
	191	ldr R7, =0x00007FFF\r
	192	ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
	193	\r
3402aac7	194	Loop2\r
bd6b9799	195	mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
bd6b9799	196	\r
3402aac7	197	Loop3\r
bd6b9799	198	orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
	199	orr R0, R0, R7, LSL R2 ; factor in the index number\r
	200	\r
	201	blx R1\r
	202	\r
	203	subs R9, R9, #1 ; decrement the way number\r
	204	bge Loop3\r
	205	subs R7, R7, #1 ; decrement the index\r
	206	bge Loop2\r
3402aac7	207	Skip\r
bd6b9799	208	add R10, R10, #2 ; increment the cache number\r
	209	cmp R3, R10\r
	210	bgt Loop1\r
3402aac7	211	\r
bd6b9799	212	Finished\r
	213	dsb\r
	214	ldmfd SP!, {r4-r12, lr}\r
	215	bx LR\r
	216	\r
efda1775	217	RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
bd6b9799	218	dmb\r
bd6b9799	219	bx LR\r
3402aac7	220	\r
efda1775	221	RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
bd6b9799	222	dsb\r
bd6b9799	223	bx LR\r
3402aac7	224	\r
efda1775	225	RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
bd6b9799	226	isb\r
	227	bx LR\r
	228	\r
efda1775	229	RVCT_ASM_EXPORT ArmReadVBar\r
836c3500	230	// Set the Address of the Vector Table in the VBAR register\r
	231	mrc p15, 0, r0, c12, c0, 0\r
	232	bx lr\r
	233	\r
efda1775	234	RVCT_ASM_EXPORT ArmWriteVBar\r
bd6b9799	235	// Set the Address of the Vector Table in the VBAR register\r
3402aac7	236	mcr p15, 0, r0, c12, c0, 0\r
bd6b9799	237	// Ensure the SCTLR.V bit is clear\r
	238	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	239	bic r0, r0, #0x00002000 ; clear V bit\r
	240	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	241	isb\r
	242	bx lr\r
	243	\r
efda1775	244	RVCT_ASM_EXPORT ArmEnableVFP\r
bd6b9799	245	// Read CPACR (Coprocessor Access Control Register)\r
	246	mrc p15, 0, r0, c1, c0, 2\r
	247	// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
	248	orr r0, r0, #0x00f00000\r
	249	// Write back CPACR (Coprocessor Access Control Register)\r
	250	mcr p15, 0, r0, c1, c0, 2\r
18029bb9	251	isb\r
bd6b9799	252	// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
	253	mov r0, #0x40000000\r
	254	mcr p10,#0x7,r0,c8,c0,#0\r
	255	bx lr\r
	256	\r
efda1775	257	RVCT_ASM_EXPORT ArmCallWFI\r
bd6b9799	258	wfi\r
	259	bx lr\r
	260	\r
	261	//Note: Return 0 in Uniprocessor implementation\r
efda1775	262	RVCT_ASM_EXPORT ArmReadCbar\r
bd6b9799	263	mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
	264	bx lr\r
	265	\r
efda1775	266	RVCT_ASM_EXPORT ArmReadMpidr\r
bd6b9799	267	mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
	268	bx lr\r
	269	\r
efda1775	270	RVCT_ASM_EXPORT ArmReadTpidrurw\r
bd6b9799	271	mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
	272	bx lr\r
	273	\r
efda1775	274	RVCT_ASM_EXPORT ArmWriteTpidrurw\r
bd6b9799	275	mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
	276	bx lr\r
	277	\r
efda1775	278	RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
bd6b9799	279	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
	280	and r0, r0, #0x000F0000\r
	281	bx lr\r
	282	\r
efda1775	283	RVCT_ASM_EXPORT ArmReadIdPfr1\r
bd6b9799	284	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
	285	bx lr\r
	286	\r
efda1775	287	RVCT_ASM_EXPORT ArmReadIdMmfr0\r
63dbd629 AB	288	mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
	289	bx lr\r
	290	\r
bd6b9799	291	END\r