[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
    EXPORT  ArmInvalidateInstructionCache\r
    EXPORT  ArmInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmCleanDataCacheEntryByMVA\r
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmCleanDataCacheEntryBySetWay\r
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmDrainWriteBuffer\r
    EXPORT  ArmEnableMmu\r
    EXPORT  ArmDisableMmu\r
    EXPORT  ArmDisableCachesAndMmu\r
    EXPORT  ArmMmuEnabled\r
    EXPORT  ArmEnableDataCache\r
    EXPORT  ArmDisableDataCache\r
    EXPORT  ArmEnableInstructionCache\r
    EXPORT  ArmDisableInstructionCache\r
    EXPORT  ArmEnableSWPInstruction\r
    EXPORT  ArmEnableBranchPrediction\r
    EXPORT  ArmDisableBranchPrediction\r
    EXPORT  ArmSetLowVectors\r
    EXPORT  ArmSetHighVectors\r
    EXPORT  ArmV7AllDataCachesOperation\r
    EXPORT  ArmDataMemoryBarrier\r
    EXPORT  ArmDataSynchronizationBarrier\r
    EXPORT  ArmInstructionSynchronizationBarrier\r
    EXPORT  ArmReadVBar\r
    EXPORT  ArmWriteVBar\r
    EXPORT  ArmEnableVFP\r
    EXPORT  ArmCallWFI\r
    EXPORT  ArmReadCbar\r
    EXPORT  ArmReadMpidr\r
    EXPORT  ArmReadTpidrurw\r
    EXPORT  ArmWriteTpidrurw\r
    EXPORT  ArmIsArchTimerImplemented\r
    EXPORT  ArmReadIdPfr1\r
    EXPORT  ArmReadIdMmfr0\r
\r
    AREA    ArmV7Support, CODE, READONLY\r
    PRESERVE8\r
\r
DC_ON           EQU     ( 0x1:SHL:2 )\r
IC_ON           EQU     ( 0x1:SHL:12 )\r
CTRL_M_BIT      EQU     (1 << 0)\r
CTRL_C_BIT      EQU     (1 << 2)\r
CTRL_B_BIT      EQU     (1 << 7)\r
CTRL_I_BIT      EQU     (1 << 12)\r
\r
\r
ArmInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
  bx      lr\r
\r
ArmCleanDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
  bx      lr\r
\r
\r
ArmInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
  bx      lr\r
\r
\r
ArmCleanDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
  bx      lr\r
\r
\r
ArmInvalidateInstructionCache\r
  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
  isb\r
  bx      LR\r
\r
ArmEnableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
\r
  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB\r
  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableCachesAndMmu\r
  mrc   p15, 0, r0, c1, c0, 0           ; Get control register\r
  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU\r
  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache\r
  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache\r
  mcr   p15, 0, r0, c1, c0, 0           ; Write control register\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmMmuEnabled\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  and     R0,R0,#1\r
  bx      LR\r
\r
ArmEnableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmEnableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmEnableSWPInstruction\r
  mrc     p15, 0, r0, c1, c0, 0\r
  orr     r0, r0, #0x00000400\r
  mcr     p15, 0, r0, c1, c0, 0\r
  isb\r
  bx      LR\r
\r
ArmEnableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmSetLowVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmSetHighVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00002000   ; Set V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmV7AllDataCachesOperation\r
  stmfd SP!,{r4-r12, LR}\r
  mov   R1, R0                ; Save Function call in R1\r
  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)\r
  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)\r
  beq   Finished\r
  mov   R10, #0\r
\r
Loop1\r
  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
  and   R12, R12, #7            ; get those 3 bits alone\r
  cmp   R12, #2\r
  blt   Skip                    ; no cache or only instruction cache at this level\r
  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
  isb                           ; isb to sync the change to the CacheSizeID reg\r
  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
  and   R2, R12, #&7            ; extract the line length field\r
  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
  ldr   R4, =0x3FF\r
  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)\r
  clz   R5, R4                  ; R5 is the bit position of the way size increment\r
  ldr   R7, =0x00007FFF\r
  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
\r
Loop2\r
  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
\r
Loop3\r
  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
  orr   R0, R0, R7, LSL R2      ; factor in the index number\r
\r
  blx   R1\r
\r
  subs  R9, R9, #1              ; decrement the way number\r
  bge   Loop3\r
  subs  R7, R7, #1              ; decrement the index\r
  bge   Loop2\r
Skip\r
  add   R10, R10, #2            ; increment the cache number\r
  cmp   R3, R10\r
  bgt   Loop1\r
\r
Finished\r
  dsb\r
  ldmfd SP!, {r4-r12, lr}\r
  bx    LR\r
\r
ArmDataMemoryBarrier\r
  dmb\r
  bx      LR\r
\r
ArmDataSynchronizationBarrier\r
ArmDrainWriteBuffer\r
  dsb\r
  bx      LR\r
\r
ArmInstructionSynchronizationBarrier\r
  isb\r
  bx      LR\r
\r
ArmReadVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mrc     p15, 0, r0, c12, c0, 0\r
  bx      lr\r
\r
ArmWriteVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mcr     p15, 0, r0, c12, c0, 0\r
  // Ensure the SCTLR.V bit is clear\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      lr\r
\r
ArmEnableVFP\r
  // Read CPACR (Coprocessor Access Control Register)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
  orr     r0, r0, #0x00f00000\r
  // Write back CPACR (Coprocessor Access Control Register)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  isb\r
  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
  mov     r0, #0x40000000\r
  mcr     p10,#0x7,r0,c8,c0,#0\r
  bx      lr\r
\r
ArmCallWFI\r
  wfi\r
  bx      lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
ArmReadCbar\r
  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register\r
  bx      lr\r
\r
ArmReadMpidr\r
  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR\r
  bx      lr\r
\r
ArmReadTpidrurw\r
  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW\r
  bx      lr\r
\r
ArmWriteTpidrurw\r
  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW\r
  bx      lr\r
\r
ArmIsArchTimerImplemented\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1\r
  and    r0, r0, #0x000F0000\r
  bx     lr\r
\r
ArmReadIdPfr1\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register\r
  bx     lr\r
\r
ArmReadIdMmfr0\r
  mrc    p15, 0, r0, c0, c1, 4     ; Read ID_MMFR0 Register\r
  bx     lr\r
\r
 END\r
Commit	Line	Data
3402aac7	1	//------------------------------------------------------------------------------\r
bd6b9799	2	//\r
bd6b9799	3	// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
9401d6f4	4	// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
bd6b9799	5	//\r
	6	// This program and the accompanying materials\r
	7	// are licensed and made available under the terms and conditions of the BSD License\r
	8	// which accompanies this distribution. The full text of the license may be found at\r
	9	// http://opensource.org/licenses/bsd-license.php\r
	10	//\r
	11	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	//\r
	14	//------------------------------------------------------------------------------\r
	15	\r
	16	EXPORT ArmInvalidateInstructionCache\r
	17	EXPORT ArmInvalidateDataCacheEntryByMVA\r
	18	EXPORT ArmCleanDataCacheEntryByMVA\r
	19	EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
	20	EXPORT ArmInvalidateDataCacheEntryBySetWay\r
	21	EXPORT ArmCleanDataCacheEntryBySetWay\r
	22	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
	23	EXPORT ArmDrainWriteBuffer\r
	24	EXPORT ArmEnableMmu\r
	25	EXPORT ArmDisableMmu\r
	26	EXPORT ArmDisableCachesAndMmu\r
	27	EXPORT ArmMmuEnabled\r
	28	EXPORT ArmEnableDataCache\r
	29	EXPORT ArmDisableDataCache\r
	30	EXPORT ArmEnableInstructionCache\r
	31	EXPORT ArmDisableInstructionCache\r
	32	EXPORT ArmEnableSWPInstruction\r
	33	EXPORT ArmEnableBranchPrediction\r
	34	EXPORT ArmDisableBranchPrediction\r
	35	EXPORT ArmSetLowVectors\r
	36	EXPORT ArmSetHighVectors\r
	37	EXPORT ArmV7AllDataCachesOperation\r
	38	EXPORT ArmDataMemoryBarrier\r
cf93a378	39	EXPORT ArmDataSynchronizationBarrier\r
bd6b9799	40	EXPORT ArmInstructionSynchronizationBarrier\r
836c3500	41	EXPORT ArmReadVBar\r
bd6b9799	42	EXPORT ArmWriteVBar\r
	43	EXPORT ArmEnableVFP\r
	44	EXPORT ArmCallWFI\r
	45	EXPORT ArmReadCbar\r
bd6b9799	46	EXPORT ArmReadMpidr\r
	47	EXPORT ArmReadTpidrurw\r
	48	EXPORT ArmWriteTpidrurw\r
	49	EXPORT ArmIsArchTimerImplemented\r
	50	EXPORT ArmReadIdPfr1\r
63dbd629	51	EXPORT ArmReadIdMmfr0\r
bd6b9799	52	\r
	53	AREA ArmV7Support, CODE, READONLY\r
	54	PRESERVE8\r
	55	\r
	56	DC_ON EQU ( 0x1:SHL:2 )\r
	57	IC_ON EQU ( 0x1:SHL:12 )\r
	58	CTRL_M_BIT EQU (1 << 0)\r
	59	CTRL_C_BIT EQU (1 << 2)\r
	60	CTRL_B_BIT EQU (1 << 7)\r
	61	CTRL_I_BIT EQU (1 << 12)\r
	62	\r
	63	\r
	64	ArmInvalidateDataCacheEntryByMVA\r
3402aac7	65	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
bd6b9799	66	bx lr\r
	67	\r
	68	ArmCleanDataCacheEntryByMVA\r
3402aac7	69	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
bd6b9799	70	bx lr\r
	71	\r
	72	\r
	73	ArmCleanInvalidateDataCacheEntryByMVA\r
	74	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
bd6b9799	75	bx lr\r
	76	\r
	77	\r
	78	ArmInvalidateDataCacheEntryBySetWay\r
3402aac7	79	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
bd6b9799	80	bx lr\r
	81	\r
	82	\r
	83	ArmCleanInvalidateDataCacheEntryBySetWay\r
3402aac7	84	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
bd6b9799	85	bx lr\r
	86	\r
	87	\r
	88	ArmCleanDataCacheEntryBySetWay\r
3402aac7	89	mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
bd6b9799	90	bx lr\r
	91	\r
	92	\r
	93	ArmInvalidateInstructionCache\r
	94	mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
	95	isb\r
	96	bx LR\r
	97	\r
	98	ArmEnableMmu\r
	99	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	100	orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
	101	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	102	dsb\r
	103	isb\r
	104	bx LR\r
	105	\r
	106	ArmDisableMmu\r
	107	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	108	bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
	109	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	110	\r
	111	mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
	112	mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
	113	dsb\r
	114	isb\r
	115	bx LR\r
	116	\r
	117	ArmDisableCachesAndMmu\r
	118	mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
	119	bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
	120	bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
	121	bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
	122	mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
	123	dsb\r
	124	isb\r
	125	bx LR\r
	126	\r
	127	ArmMmuEnabled\r
	128	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	129	and R0,R0,#1\r
	130	bx LR\r
	131	\r
	132	ArmEnableDataCache\r
	133	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	134	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	135	orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
	136	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	137	dsb\r
	138	isb\r
	139	bx LR\r
3402aac7	140	\r
bd6b9799	141	ArmDisableDataCache\r
	142	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	143	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	144	bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
	145	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	146	dsb\r
	147	isb\r
	148	bx LR\r
	149	\r
	150	ArmEnableInstructionCache\r
	151	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	152	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	153	orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
	154	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	155	dsb\r
	156	isb\r
	157	bx LR\r
3402aac7	158	\r
bd6b9799	159	ArmDisableInstructionCache\r
	160	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	161	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	162	BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
	163	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	164	isb\r
	165	bx LR\r
	166	\r
	167	ArmEnableSWPInstruction\r
	168	mrc p15, 0, r0, c1, c0, 0\r
	169	orr r0, r0, #0x00000400\r
	170	mcr p15, 0, r0, c1, c0, 0\r
	171	isb\r
	172	bx LR\r
	173	\r
	174	ArmEnableBranchPrediction\r
	175	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	176	orr r0, r0, #0x00000800 ;\r
	177	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	178	dsb\r
	179	isb\r
	180	bx LR\r
	181	\r
	182	ArmDisableBranchPrediction\r
	183	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	184	bic r0, r0, #0x00000800 ;\r
	185	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	186	dsb\r
	187	isb\r
	188	bx LR\r
	189	\r
	190	ArmSetLowVectors\r
	191	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	192	bic r0, r0, #0x00002000 ; clear V bit\r
	193	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	194	isb\r
	195	bx LR\r
	196	\r
	197	ArmSetHighVectors\r
	198	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
c6ba1c12	199	orr r0, r0, #0x00002000 ; Set V bit\r
bd6b9799	200	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	201	isb\r
	202	bx LR\r
	203	\r
	204	ArmV7AllDataCachesOperation\r
	205	stmfd SP!,{r4-r12, LR}\r
	206	mov R1, R0 ; Save Function call in R1\r
	207	mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
	208	ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
	209	mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
	210	beq Finished\r
	211	mov R10, #0\r
	212	\r
3402aac7	213	Loop1\r
bd6b9799	214	add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
	215	mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
	216	and R12, R12, #7 ; get those 3 bits alone\r
	217	cmp R12, #2\r
	218	blt Skip ; no cache or only instruction cache at this level\r
	219	mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
3402aac7	220	isb ; isb to sync the change to the CacheSizeID reg\r
bd6b9799	221	mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
	222	and R2, R12, #&7 ; extract the line length field\r
	223	add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
	224	ldr R4, =0x3FF\r
	225	ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
	226	clz R5, R4 ; R5 is the bit position of the way size increment\r
	227	ldr R7, =0x00007FFF\r
	228	ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
	229	\r
3402aac7	230	Loop2\r
bd6b9799	231	mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
bd6b9799	232	\r
3402aac7	233	Loop3\r
bd6b9799	234	orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
	235	orr R0, R0, R7, LSL R2 ; factor in the index number\r
	236	\r
	237	blx R1\r
	238	\r
	239	subs R9, R9, #1 ; decrement the way number\r
	240	bge Loop3\r
	241	subs R7, R7, #1 ; decrement the index\r
	242	bge Loop2\r
3402aac7	243	Skip\r
bd6b9799	244	add R10, R10, #2 ; increment the cache number\r
	245	cmp R3, R10\r
	246	bgt Loop1\r
3402aac7	247	\r
bd6b9799	248	Finished\r
	249	dsb\r
	250	ldmfd SP!, {r4-r12, lr}\r
	251	bx LR\r
	252	\r
	253	ArmDataMemoryBarrier\r
	254	dmb\r
	255	bx LR\r
3402aac7	256	\r
cf93a378	257	ArmDataSynchronizationBarrier\r
bd6b9799	258	ArmDrainWriteBuffer\r
	259	dsb\r
	260	bx LR\r
3402aac7	261	\r
bd6b9799	262	ArmInstructionSynchronizationBarrier\r
	263	isb\r
	264	bx LR\r
	265	\r
836c3500	266	ArmReadVBar\r
	267	// Set the Address of the Vector Table in the VBAR register\r
	268	mrc p15, 0, r0, c12, c0, 0\r
	269	bx lr\r
	270	\r
bd6b9799	271	ArmWriteVBar\r
bd6b9799	272	// Set the Address of the Vector Table in the VBAR register\r
3402aac7	273	mcr p15, 0, r0, c12, c0, 0\r
bd6b9799	274	// Ensure the SCTLR.V bit is clear\r
	275	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	276	bic r0, r0, #0x00002000 ; clear V bit\r
	277	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	278	isb\r
	279	bx lr\r
	280	\r
	281	ArmEnableVFP\r
	282	// Read CPACR (Coprocessor Access Control Register)\r
	283	mrc p15, 0, r0, c1, c0, 2\r
	284	// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
	285	orr r0, r0, #0x00f00000\r
	286	// Write back CPACR (Coprocessor Access Control Register)\r
	287	mcr p15, 0, r0, c1, c0, 2\r
18029bb9	288	isb\r
bd6b9799	289	// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
	290	mov r0, #0x40000000\r
	291	mcr p10,#0x7,r0,c8,c0,#0\r
	292	bx lr\r
	293	\r
	294	ArmCallWFI\r
	295	wfi\r
	296	bx lr\r
	297	\r
	298	//Note: Return 0 in Uniprocessor implementation\r
	299	ArmReadCbar\r
	300	mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
	301	bx lr\r
	302	\r
bd6b9799	303	ArmReadMpidr\r
	304	mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
	305	bx lr\r
	306	\r
	307	ArmReadTpidrurw\r
	308	mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
	309	bx lr\r
	310	\r
	311	ArmWriteTpidrurw\r
	312	mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
	313	bx lr\r
	314	\r
	315	ArmIsArchTimerImplemented\r
	316	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
	317	and r0, r0, #0x000F0000\r
	318	bx lr\r
	319	\r
	320	ArmReadIdPfr1\r
	321	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
	322	bx lr\r
	323	\r
63dbd629 AB	324	ArmReadIdMmfr0\r
	325	mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
	326	bx lr\r
	327	\r
bd6b9799	328	END\r