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93deac7e HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
07783fdd | 4 | # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
93deac7e HL |
5 | #\r |
6 | # This program and the accompanying materials\r | |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <AsmMacroIoLibV8.h>\r | |
17 | \r | |
18 | .text\r | |
19 | .align 3\r | |
f6c5a29b | 20 | GCC_ASM_EXPORT (ArmReadMidr)\r |
93deac7e HL |
21 | GCC_ASM_EXPORT (ArmCacheInfo)\r |
22 | GCC_ASM_EXPORT (ArmGetInterruptState)\r | |
23 | GCC_ASM_EXPORT (ArmGetFiqState)\r | |
24 | GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)\r | |
25 | GCC_ASM_EXPORT (ArmSetTTBR0)\r | |
26 | GCC_ASM_EXPORT (ArmGetTCR)\r | |
27 | GCC_ASM_EXPORT (ArmSetTCR)\r | |
28 | GCC_ASM_EXPORT (ArmGetMAIR)\r | |
29 | GCC_ASM_EXPORT (ArmSetMAIR)\r | |
30 | GCC_ASM_EXPORT (ArmWriteCpacr)\r | |
31 | GCC_ASM_EXPORT (ArmWriteAuxCr)\r | |
32 | GCC_ASM_EXPORT (ArmReadAuxCr)\r | |
33 | GCC_ASM_EXPORT (ArmInvalidateTlb)\r | |
34 | GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)\r | |
d6dc67ba | 35 | GCC_ASM_EXPORT (ArmWriteCptr)\r |
93deac7e HL |
36 | GCC_ASM_EXPORT (ArmWriteScr)\r |
37 | GCC_ASM_EXPORT (ArmWriteMVBar)\r | |
38 | GCC_ASM_EXPORT (ArmCallWFE)\r | |
39 | GCC_ASM_EXPORT (ArmCallSEV)\r | |
52d44f77 OM |
40 | GCC_ASM_EXPORT (ArmReadCpuActlr)\r |
41 | GCC_ASM_EXPORT (ArmWriteCpuActlr)\r | |
07783fdd | 42 | GCC_ASM_EXPORT (ArmReadSctlr)\r |
93deac7e HL |
43 | \r |
44 | #------------------------------------------------------------------------------\r | |
45 | \r | |
4af3dd80 EC |
46 | .set DAIF_RD_FIQ_BIT, (1 << 6)\r |
47 | .set DAIF_RD_IRQ_BIT, (1 << 7)\r | |
93deac7e | 48 | \r |
f6c5a29b | 49 | ASM_PFX(ArmReadMidr):\r |
93deac7e HL |
50 | mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r |
51 | ret\r | |
52 | \r | |
53 | ASM_PFX(ArmCacheInfo):\r | |
54 | mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)\r | |
55 | ret\r | |
56 | \r | |
57 | ASM_PFX(ArmGetInterruptState):\r | |
58 | mrs x0, daif\r | |
4af3dd80 EC |
59 | tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)\r |
60 | cset w0, eq // if Z=1 return 1, else 0\r | |
93deac7e HL |
61 | ret\r |
62 | \r | |
63 | ASM_PFX(ArmGetFiqState):\r | |
64 | mrs x0, daif\r | |
4af3dd80 EC |
65 | tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)\r |
66 | cset w0, eq // if Z=1 return 1, else 0\r | |
93deac7e HL |
67 | ret\r |
68 | \r | |
69 | ASM_PFX(ArmWriteCpacr):\r | |
70 | msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)\r | |
71 | ret\r | |
72 | \r | |
73 | ASM_PFX(ArmWriteAuxCr):\r | |
74 | EL1_OR_EL2(x1)\r | |
75 | 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
27995cd5 | 76 | ret\r |
93deac7e | 77 | 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r |
27995cd5 | 78 | ret\r |
93deac7e HL |
79 | \r |
80 | ASM_PFX(ArmReadAuxCr):\r | |
81 | EL1_OR_EL2(x1)\r | |
82 | 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r | |
27995cd5 | 83 | ret\r |
93deac7e | 84 | 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3\r |
27995cd5 | 85 | ret\r |
93deac7e HL |
86 | \r |
87 | ASM_PFX(ArmSetTTBR0):\r | |
88 | EL1_OR_EL2_OR_EL3(x1)\r | |
89 | 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
90 | b 4f\r | |
91 | 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
92 | b 4f\r | |
93 | 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)\r | |
94 | 4:isb\r | |
95 | ret\r | |
96 | \r | |
97 | ASM_PFX(ArmGetTTBR0BaseAddress):\r | |
98 | EL1_OR_EL2(x1)\r | |
99 | 1:mrs x0, ttbr0_el1\r | |
100 | b 3f\r | |
101 | 2:mrs x0, ttbr0_el2\r | |
102 | 3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */\r | |
103 | and x0, x0, x1\r | |
104 | isb\r | |
105 | ret\r | |
106 | \r | |
107 | ASM_PFX(ArmGetTCR):\r | |
108 | EL1_OR_EL2_OR_EL3(x1)\r | |
109 | 1:mrs x0, tcr_el1\r | |
110 | b 4f\r | |
111 | 2:mrs x0, tcr_el2\r | |
112 | b 4f\r | |
113 | 3:mrs x0, tcr_el3\r | |
114 | 4:isb\r | |
115 | ret\r | |
116 | \r | |
117 | ASM_PFX(ArmSetTCR):\r | |
118 | EL1_OR_EL2_OR_EL3(x1)\r | |
119 | 1:msr tcr_el1, x0\r | |
120 | b 4f\r | |
121 | 2:msr tcr_el2, x0\r | |
122 | b 4f\r | |
123 | 3:msr tcr_el3, x0\r | |
124 | 4:isb\r | |
125 | ret\r | |
126 | \r | |
127 | ASM_PFX(ArmGetMAIR):\r | |
128 | EL1_OR_EL2_OR_EL3(x1)\r | |
129 | 1:mrs x0, mair_el1\r | |
130 | b 4f\r | |
131 | 2:mrs x0, mair_el2\r | |
132 | b 4f\r | |
133 | 3:mrs x0, mair_el3\r | |
134 | 4:isb\r | |
135 | ret\r | |
136 | \r | |
137 | ASM_PFX(ArmSetMAIR):\r | |
138 | EL1_OR_EL2_OR_EL3(x1)\r | |
139 | 1:msr mair_el1, x0\r | |
140 | b 4f\r | |
141 | 2:msr mair_el2, x0\r | |
142 | b 4f\r | |
143 | 3:msr mair_el3, x0\r | |
144 | 4:isb\r | |
145 | ret\r | |
146 | \r | |
147 | \r | |
148 | //\r | |
149 | //VOID\r | |
150 | //ArmUpdateTranslationTableEntry (\r | |
151 | // IN VOID *TranslationTableEntry // X0\r | |
152 | // IN VOID *MVA // X1\r | |
153 | // );\r | |
154 | ASM_PFX(ArmUpdateTranslationTableEntry):\r | |
155 | dc civac, x0 // Clean and invalidate data line\r | |
156 | dsb sy\r | |
157 | EL1_OR_EL2_OR_EL3(x0)\r | |
158 | 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1\r | |
159 | b 4f\r | |
160 | 2: tlbi vae2, x1 // TLB Invalidate VA , EL2\r | |
161 | b 4f\r | |
162 | 3: tlbi vae3, x1 // TLB Invalidate VA , EL3\r | |
163 | 4: dsb sy\r | |
164 | isb\r | |
165 | ret\r | |
166 | \r | |
167 | ASM_PFX(ArmInvalidateTlb):\r | |
168 | EL1_OR_EL2_OR_EL3(x0)\r | |
70f89c0b | 169 | 1: tlbi vmalle1\r |
93deac7e HL |
170 | b 4f\r |
171 | 2: tlbi alle2\r | |
172 | b 4f\r | |
173 | 3: tlbi alle3\r | |
174 | 4: dsb sy\r | |
175 | isb\r | |
176 | ret\r | |
177 | \r | |
d6dc67ba | 178 | ASM_PFX(ArmWriteCptr):\r |
93deac7e | 179 | msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)\r |
d6dc67ba | 180 | ret\r |
93deac7e HL |
181 | \r |
182 | ASM_PFX(ArmWriteScr):\r | |
183 | msr scr_el3, x0 // Secure configuration register EL3\r | |
b2d0e0c5 | 184 | isb\r |
93deac7e HL |
185 | ret\r |
186 | \r | |
187 | ASM_PFX(ArmWriteMVBar):\r | |
27995cd5 | 188 | msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3\r |
93deac7e HL |
189 | ret\r |
190 | \r | |
191 | ASM_PFX(ArmCallWFE):\r | |
192 | wfe\r | |
193 | ret\r | |
194 | \r | |
195 | ASM_PFX(ArmCallSEV):\r | |
196 | sev\r | |
197 | ret\r | |
198 | \r | |
52d44f77 OM |
199 | ASM_PFX(ArmReadCpuActlr):\r |
200 | mrs x0, S3_1_c15_c2_0\r | |
201 | ret\r | |
202 | \r | |
203 | ASM_PFX(ArmWriteCpuActlr):\r | |
204 | msr S3_1_c15_c2_0, x0\r | |
205 | dsb sy\r | |
206 | isb\r | |
207 | ret\r | |
93deac7e | 208 | \r |
07783fdd SV |
209 | ASM_PFX(ArmReadSctlr):\r |
210 | EL1_OR_EL2_OR_EL3(x1)\r | |
211 | 1:mrs x0, sctlr_el1\r | |
212 | ret\r | |
213 | 2:mrs x0, sctlr_el2\r | |
214 | ret\r | |
215 | 3:mrs x0, sctlr_el3\r | |
216 | 4:ret\r | |
217 | \r | |
93deac7e | 218 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |