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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
f6c5a29b | 4 | // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
6 | // This program and the accompanying materials\r | |
7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
8 | // which accompanies this distribution. The full text of the license may be found at\r | |
9 | // http://opensource.org/licenses/bsd-license.php\r | |
10 | //\r | |
11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | //\r | |
14 | //------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <AsmMacroIoLib.h>\r | |
3402aac7 | 17 | \r |
bd6b9799 | 18 | INCLUDE AsmMacroIoLib.inc\r |
19 | \r | |
f6c5a29b | 20 | EXPORT ArmReadMidr\r |
64751727 | 21 | EXPORT ArmCacheInfo\r |
bd6b9799 | 22 | EXPORT ArmGetInterruptState\r |
23 | EXPORT ArmGetFiqState\r | |
24 | EXPORT ArmGetTTBR0BaseAddress\r | |
25 | EXPORT ArmSetTTBR0\r | |
26 | EXPORT ArmSetDomainAccessControl\r | |
27 | EXPORT CPSRMaskInsert\r | |
28 | EXPORT CPSRRead\r | |
836c3500 | 29 | EXPORT ArmReadCpacr\r |
30 | EXPORT ArmWriteCpacr\r | |
bd6b9799 | 31 | EXPORT ArmWriteAuxCr\r |
32 | EXPORT ArmReadAuxCr\r | |
33 | EXPORT ArmInvalidateTlb\r | |
34 | EXPORT ArmUpdateTranslationTableEntry\r | |
836c3500 | 35 | EXPORT ArmReadScr\r |
bd6b9799 | 36 | EXPORT ArmWriteScr\r |
836c3500 | 37 | EXPORT ArmReadMVBar\r |
38 | EXPORT ArmWriteMVBar\r | |
5ea2c2d3 | 39 | EXPORT ArmReadHVBar\r |
40 | EXPORT ArmWriteHVBar\r | |
b1d41be7 | 41 | EXPORT ArmCallWFE\r |
42 | EXPORT ArmCallSEV\r | |
836c3500 | 43 | EXPORT ArmReadSctlr\r |
52d44f77 OM |
44 | EXPORT ArmReadCpuActlr\r |
45 | EXPORT ArmWriteCpuActlr\r | |
bd6b9799 | 46 | \r |
47 | AREA ArmLibSupport, CODE, READONLY\r | |
48 | \r | |
f6c5a29b | 49 | ArmReadMidr\r |
bd6b9799 | 50 | mrc p15,0,R0,c0,c0,0\r |
51 | bx LR\r | |
52 | \r | |
64751727 | 53 | ArmCacheInfo\r |
bd6b9799 | 54 | mrc p15,0,R0,c0,c0,1\r |
55 | bx LR\r | |
56 | \r | |
57 | ArmGetInterruptState\r | |
58 | mrs R0,CPSR\r | |
59 | tst R0,#0x80 // Check if IRQ is enabled.\r | |
60 | moveq R0,#1\r | |
61 | movne R0,#0\r | |
62 | bx LR\r | |
63 | \r | |
64 | ArmGetFiqState\r | |
65 | mrs R0,CPSR\r | |
66 | tst R0,#0x40 // Check if FIQ is enabled.\r | |
67 | moveq R0,#1\r | |
68 | movne R0,#0\r | |
69 | bx LR\r | |
70 | \r | |
71 | ArmSetDomainAccessControl\r | |
72 | mcr p15,0,r0,c3,c0,0\r | |
73 | bx lr\r | |
74 | \r | |
75 | CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert\r | |
76 | stmfd sp!, {r4-r12, lr} // save all the banked registers\r | |
77 | mov r3, sp // copy the stack pointer into a non-banked register\r | |
78 | mrs r2, cpsr // read the cpsr\r | |
79 | bic r2, r2, r0 // clear mask in the cpsr\r | |
80 | and r1, r1, r0 // clear bits outside the mask in the input\r | |
81 | orr r2, r2, r1 // set field\r | |
82 | msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r | |
83 | isb\r | |
84 | mov sp, r3 // restore stack pointer\r | |
85 | ldmfd sp!, {r4-r12, lr} // restore registers\r | |
86 | bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r | |
87 | \r | |
88 | CPSRRead\r | |
89 | mrs r0, cpsr\r | |
90 | bx lr\r | |
91 | \r | |
836c3500 | 92 | ArmReadCpacr\r |
93 | mrc p15, 0, r0, c1, c0, 2\r | |
94 | bx lr\r | |
95 | \r | |
96 | ArmWriteCpacr\r | |
bd6b9799 | 97 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 98 | isb\r |
bd6b9799 | 99 | bx lr\r |
100 | \r | |
101 | ArmWriteAuxCr\r | |
102 | mcr p15, 0, r0, c1, c0, 1\r | |
103 | bx lr\r | |
104 | \r | |
105 | ArmReadAuxCr\r | |
106 | mrc p15, 0, r0, c1, c0, 1\r | |
3402aac7 | 107 | bx lr\r |
bd6b9799 | 108 | \r |
109 | ArmSetTTBR0\r | |
110 | mcr p15,0,r0,c2,c0,0\r | |
111 | isb\r | |
112 | bx lr\r | |
113 | \r | |
114 | ArmGetTTBR0BaseAddress\r | |
115 | mrc p15,0,r0,c2,c0,0\r | |
116 | LoadConstantToReg(0xFFFFC000, r1)\r | |
117 | and r0, r0, r1\r | |
118 | isb\r | |
119 | bx lr\r | |
120 | \r | |
121 | //\r | |
122 | //VOID\r | |
123 | //ArmUpdateTranslationTableEntry (\r | |
124 | // IN VOID *TranslationTableEntry // R0\r | |
125 | // IN VOID *MVA // R1\r | |
126 | // );\r | |
127 | ArmUpdateTranslationTableEntry\r | |
128 | mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r | |
129 | dsb\r | |
130 | mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r | |
131 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
132 | dsb\r | |
133 | isb\r | |
134 | bx lr\r | |
135 | \r | |
136 | ArmInvalidateTlb\r | |
137 | mov r0,#0\r | |
138 | mcr p15,0,r0,c8,c7,0\r | |
139 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
140 | dsb\r | |
141 | isb\r | |
142 | bx lr\r | |
143 | \r | |
836c3500 | 144 | ArmReadScr\r |
145 | mrc p15, 0, r0, c1, c1, 0\r | |
146 | bx lr\r | |
147 | \r | |
bd6b9799 | 148 | ArmWriteScr\r |
149 | mcr p15, 0, r0, c1, c1, 0\r | |
150 | bx lr\r | |
151 | \r | |
5ea2c2d3 | 152 | ArmReadHVBar\r |
153 | mrc p15, 4, r0, c12, c0, 0\r | |
154 | bx lr\r | |
155 | \r | |
156 | ArmWriteHVBar\r | |
157 | mcr p15, 4, r0, c12, c0, 0\r | |
158 | bx lr\r | |
159 | \r | |
836c3500 | 160 | ArmReadMVBar\r |
161 | mrc p15, 0, r0, c12, c0, 1\r | |
162 | bx lr\r | |
163 | \r | |
164 | ArmWriteMVBar\r | |
bd6b9799 | 165 | mcr p15, 0, r0, c12, c0, 1\r |
166 | bx lr\r | |
3402aac7 | 167 | \r |
b1d41be7 | 168 | ArmCallWFE\r |
169 | wfe\r | |
27995cd5 | 170 | bx lr\r |
b1d41be7 | 171 | \r |
172 | ArmCallSEV\r | |
173 | sev\r | |
27995cd5 | 174 | bx lr\r |
b1d41be7 | 175 | \r |
836c3500 | 176 | ArmReadSctlr\r |
27995cd5 | 177 | mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r |
91c38d4e | 178 | bx lr\r |
52d44f77 OM |
179 | \r |
180 | \r | |
181 | ArmReadCpuActlr\r | |
182 | mrc p15, 0, r0, c1, c0, 1\r | |
183 | bx lr\r | |
184 | \r | |
185 | ArmWriteCpuActlr\r | |
186 | mcr p15, 0, r0, c1, c0, 1\r | |
187 | dsb\r | |
188 | isb\r | |
189 | bx lr\r | |
836c3500 | 190 | \r |
bd6b9799 | 191 | END\r |