projects / mirror_edk2.git / blame
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|---|---|---|
| 2ef2b01e A |
1 | /** @file\r |
| 2 | \r | |
| d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 836c3500 | 4 | Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r |
| 2ef2b01e | 5 | \r |
| d6ebcab7 | 6 | This program and the accompanying materials\r |
| 2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #include <Base.h>\r | |
| 17 | \r | |
| 18 | #include <Library/ArmLib.h>\r | |
| 19 | #include <Library/DebugLib.h>\r | |
| 20 | #include <Library/PcdLib.h>\r | |
| 21 | \r | |
| 22 | #include "ArmLibPrivate.h"\r | |
| 23 | \r | |
| 24 | VOID\r | |
| 25 | EFIAPI\r | |
| 26 | ArmCacheInformation (\r | |
| 27 | OUT ARM_CACHE_INFO *CacheInfo\r | |
| 28 | )\r | |
| 29 | {\r | |
| 30 | if (CacheInfo != NULL) {\r | |
| 31 | CacheInfo->Type = ArmCacheType();\r | |
| 32 | CacheInfo->Architecture = ArmCacheArchitecture();\r | |
| 33 | CacheInfo->DataCachePresent = ArmDataCachePresent();\r | |
| 34 | CacheInfo->DataCacheSize = ArmDataCacheSize();\r | |
| 35 | CacheInfo->DataCacheAssociativity = ArmDataCacheAssociativity();\r | |
| 36 | CacheInfo->DataCacheLineLength = ArmDataCacheLineLength();\r | |
| 37 | CacheInfo->InstructionCachePresent = ArmInstructionCachePresent();\r | |
| 38 | CacheInfo->InstructionCacheSize = ArmInstructionCacheSize();\r | |
| 39 | CacheInfo->InstructionCacheAssociativity = ArmInstructionCacheAssociativity();\r | |
| 40 | CacheInfo->InstructionCacheLineLength = ArmInstructionCacheLineLength();\r | |
| 41 | }\r | |
| 42 | }\r | |
| 43 | \r | |
| 44 | VOID\r | |
| 45 | EFIAPI\r | |
| 46 | ArmSwitchProcessorMode (\r | |
| 47 | IN ARM_PROCESSOR_MODE Mode\r | |
| 48 | )\r | |
| 49 | {\r | |
| 50 | CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);\r | |
| 51 | }\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | ARM_PROCESSOR_MODE\r | |
| 55 | EFIAPI\r | |
| 56 | ArmProcessorMode (\r | |
| 57 | VOID\r | |
| 58 | )\r | |
| 59 | {\r | |
| 60 | return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);\r | |
| 61 | }\r | |
| bd6b9799 | 62 | \r |
| 63 | VOID\r | |
| 64 | EFIAPI\r | |
| 65 | ArmSetAuxCrBit (\r | |
| 66 | IN UINT32 Bits\r | |
| 67 | )\r | |
| 68 | {\r | |
| 69 | UINT32 val = ArmReadAuxCr();\r | |
| 70 | val |= Bits;\r | |
| 71 | ArmWriteAuxCr(val);\r | |
| 72 | }\r | |
| 73 | \r | |
| 836c3500 | 74 | VOID\r |
| 75 | EFIAPI\r | |
| 76 | ArmUnsetAuxCrBit (\r | |
| 77 | IN UINT32 Bits\r | |
| 78 | )\r | |
| 79 | {\r | |
| 80 | UINT32 val = ArmReadAuxCr();\r | |
| 81 | val &= ~Bits;\r | |
| 82 | ArmWriteAuxCr(val);\r | |
| 83 | }\r |