projects / mirror_edk2.git / blame
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1 | #------------------------------------------------------------------------------ |
| 2 | # | |
| d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
| 2ef2b01e | 4 | # |
| d6ebcab7 | 5 | # This program and the accompanying materials |
| 2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
| 7 | # which accompanies this distribution. The full text of the license may be found at | |
| 8 | # http://opensource.org/licenses/bsd-license.php | |
| 9 | # | |
| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
| 12 | # | |
| 13 | #------------------------------------------------------------------------------ | |
| 14 | ||
| 1bfda055 | 15 | #include <AsmMacroIoLib.h> |
| 16 | ||
| 2ef2b01e A |
17 | .text |
| 18 | .align 2 | |
| 1bfda055 | 19 | GCC_ASM_EXPORT(Cp15IdCode) |
| 20 | GCC_ASM_EXPORT(Cp15CacheInfo) | |
| 21 | GCC_ASM_EXPORT(ArmEnableInterrupts) | |
| 22 | GCC_ASM_EXPORT(ArmDisableInterrupts) | |
| 23 | GCC_ASM_EXPORT(ArmGetInterruptState) | |
| 24 | GCC_ASM_EXPORT(ArmEnableFiq) | |
| 25 | GCC_ASM_EXPORT(ArmDisableFiq) | |
| 26 | GCC_ASM_EXPORT(ArmGetFiqState) | |
| 27 | GCC_ASM_EXPORT(ArmInvalidateTlb) | |
| 28 | GCC_ASM_EXPORT(ArmSetTTBR0) | |
| 29 | GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) | |
| 30 | GCC_ASM_EXPORT(ArmSetDomainAccessControl) | |
| 31 | GCC_ASM_EXPORT(CPSRMaskInsert) | |
| 32 | GCC_ASM_EXPORT(CPSRRead) | |
| 2ef2b01e A |
33 | |
| 34 | #------------------------------------------------------------------------------ | |
| 35 | ||
| 36 | ASM_PFX(Cp15IdCode): | |
| 37 | mrc p15,0,R0,c0,c0,0 | |
| 38 | bx LR | |
| 39 | ||
| 40 | ASM_PFX(Cp15CacheInfo): | |
| 41 | mrc p15,0,R0,c0,c0,1 | |
| 42 | bx LR | |
| 43 | ||
| 44 | ASM_PFX(ArmEnableInterrupts): | |
| 2ac288f9 | 45 | mrs R0,CPSR |
| 46 | bic R0,R0,#0x80 @Enable IRQ interrupts | |
| 47 | msr CPSR_c,R0 | |
| 48 | bx LR | |
| 2ef2b01e A |
49 | |
| 50 | ASM_PFX(ArmDisableInterrupts): | |
| 2ac288f9 | 51 | mrs R0,CPSR |
| 52 | orr R1,R0,#0x80 @Disable IRQ interrupts | |
| 53 | msr CPSR_c,R1 | |
| 2ef2b01e A |
54 | tst R0,#0x80 |
| 55 | moveq R0,#1 | |
| 56 | movne R0,#0 | |
| 2ac288f9 | 57 | bx LR |
| 2ef2b01e A |
58 | |
| 59 | ASM_PFX(ArmGetInterruptState): | |
| 2ac288f9 | 60 | mrs R0,CPSR |
| 61 | tst R0,#0x80 @Check if IRQ is enabled. | |
| 62 | moveq R0,#1 | |
| 63 | movne R0,#0 | |
| 64 | bx LR | |
| 2ef2b01e | 65 | |
| 0416278c | 66 | ASM_PFX(ArmEnableFiq): |
| 2ac288f9 | 67 | mrs R0,CPSR |
| 68 | bic R0,R0,#0x40 @Enable FIQ interrupts | |
| 69 | msr CPSR_c,R0 | |
| 70 | bx LR | |
| 0416278c | 71 | |
| 72 | ASM_PFX(ArmDisableFiq): | |
| 2ac288f9 | 73 | mrs R0,CPSR |
| 74 | orr R1,R0,#0x40 @Disable FIQ interrupts | |
| 75 | msr CPSR_c,R1 | |
| 0416278c | 76 | tst R0,#0x80 |
| 77 | moveq R0,#1 | |
| 78 | movne R0,#0 | |
| 2ac288f9 | 79 | bx LR |
| 0416278c | 80 | |
| 81 | ASM_PFX(ArmGetFiqState): | |
| 2ac288f9 | 82 | mrs R0,CPSR |
| 83 | tst R0,#0x80 @Check if FIQ is enabled. | |
| 84 | moveq R0,#1 | |
| 85 | movne R0,#0 | |
| 86 | bx LR | |
| 0416278c | 87 | |
| 2ef2b01e A |
88 | ASM_PFX(ArmInvalidateTlb): |
| 89 | mov r0,#0 | |
| 90 | mcr p15,0,r0,c8,c7,0 | |
| 91 | bx lr | |
| 92 | ||
| 1bfda055 | 93 | ASM_PFX(ArmSetTTBR0): |
| 2ef2b01e A |
94 | mcr p15,0,r0,c2,c0,0 |
| 95 | bx lr | |
| 96 | ||
| 1bfda055 | 97 | ASM_PFX(ArmGetTTBR0BaseAddress): |
| c2b5ca8b | 98 | mrc p15,0,r0,c2,c0,0 |
| 1bfda055 | 99 | LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000 |
| 100 | and r0, r0, r1 | |
| c2b5ca8b A |
101 | bx lr |
| 102 | ||
| 103 | ||
| 2ef2b01e A |
104 | ASM_PFX(ArmSetDomainAccessControl): |
| 105 | mcr p15,0,r0,c3,c0,0 | |
| 106 | bx lr | |
| 107 | ||
| 108 | ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert | |
| 109 | stmfd sp!, {r4-r12, lr} @ save all the banked registers | |
| 110 | mov r3, sp @ copy the stack pointer into a non-banked register | |
| 111 | mrs r2, cpsr @ read the cpsr | |
| 112 | bic r2, r2, r0 @ clear mask in the cpsr | |
| 113 | and r1, r1, r0 @ clear bits outside the mask in the input | |
| 114 | orr r2, r2, r1 @ set field | |
| 115 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) | |
| 116 | mov sp, r3 @ restore stack pointer | |
| 117 | ldmfd sp!, {r4-r12, lr} @ restore registers | |
| 118 | bx lr @ return (hopefully thumb-safe!) | |
| 119 | ||
| 120 | ASM_PFX(CPSRRead): | |
| 121 | mrs r0, cpsr | |
| 122 | bx lr | |
| 123 | ||
| 124 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |