projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ef2b01e A |
1 | #------------------------------------------------------------------------------ |
| 2 | # | |
| d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
| 2ef2b01e | 4 | # |
| d6ebcab7 | 5 | # This program and the accompanying materials |
| 2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
| 7 | # which accompanies this distribution. The full text of the license may be found at | |
| 8 | # http://opensource.org/licenses/bsd-license.php | |
| 9 | # | |
| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
| 12 | # | |
| 13 | #------------------------------------------------------------------------------ | |
| 14 | ||
| 15 | .text | |
| 16 | .align 2 | |
| 17 | .globl ASM_PFX(Cp15IdCode) | |
| 63ca7402 | 18 | INTERWORK_FUNC(Cp15IdCode) |
| 2ef2b01e | 19 | .globl ASM_PFX(Cp15CacheInfo) |
| 63ca7402 | 20 | INTERWORK_FUNC(Cp15CacheInfo) |
| 2ef2b01e | 21 | .globl ASM_PFX(ArmEnableInterrupts) |
| 63ca7402 | 22 | INTERWORK_FUNC(ArmEnableInterrupts) |
| 2ef2b01e | 23 | .globl ASM_PFX(ArmDisableInterrupts) |
| 63ca7402 | 24 | INTERWORK_FUNC(ArmDisableInterrupts) |
| 2ef2b01e | 25 | .globl ASM_PFX(ArmGetInterruptState) |
| 63ca7402 | 26 | INTERWORK_FUNC(ArmGetInterruptState) |
| 0416278c | 27 | .globl ASM_PFX(ArmEnableFiq) |
| 63ca7402 | 28 | INTERWORK_FUNC(ArmEnableFiq) |
| 0416278c | 29 | .globl ASM_PFX(ArmDisableFiq) |
| 63ca7402 | 30 | INTERWORK_FUNC(ArmDisableFiq) |
| 0416278c | 31 | .globl ASM_PFX(ArmGetFiqState) |
| 63ca7402 | 32 | INTERWORK_FUNC(ArmGetFiqState) |
| 2ef2b01e | 33 | .globl ASM_PFX(ArmInvalidateTlb) |
| 63ca7402 | 34 | INTERWORK_FUNC(ArmInvalidateTlb) |
| 2ef2b01e | 35 | .globl ASM_PFX(ArmSetTranslationTableBaseAddress) |
| 63ca7402 | 36 | INTERWORK_FUNC(ArmSetTranslationTableBaseAddress) |
| c2b5ca8b | 37 | .globl ASM_PFX(ArmGetTranslationTableBaseAddress) |
| 63ca7402 | 38 | INTERWORK_FUNC(ArmGetTranslationTableBaseAddress) |
| 2ef2b01e | 39 | .globl ASM_PFX(ArmSetDomainAccessControl) |
| 63ca7402 | 40 | INTERWORK_FUNC(ArmSetDomainAccessControl) |
| 2ef2b01e | 41 | .globl ASM_PFX(CPSRMaskInsert) |
| 63ca7402 | 42 | INTERWORK_FUNC(CPSRMaskInsert) |
| 2ef2b01e | 43 | .globl ASM_PFX(CPSRRead) |
| 63ca7402 | 44 | INTERWORK_FUNC(CPSRRead) |
| 45 | ||
| 2ef2b01e A |
46 | |
| 47 | #------------------------------------------------------------------------------ | |
| 48 | ||
| 49 | ASM_PFX(Cp15IdCode): | |
| 50 | mrc p15,0,R0,c0,c0,0 | |
| 51 | bx LR | |
| 52 | ||
| 53 | ASM_PFX(Cp15CacheInfo): | |
| 54 | mrc p15,0,R0,c0,c0,1 | |
| 55 | bx LR | |
| 56 | ||
| 57 | ASM_PFX(ArmEnableInterrupts): | |
| 58 | mrs R0,CPSR | |
| 59 | bic R0,R0,#0x80 @Enable IRQ interrupts | |
| 60 | msr CPSR_c,R0 | |
| 61 | bx LR | |
| 62 | ||
| 63 | ASM_PFX(ArmDisableInterrupts): | |
| 64 | mrs R0,CPSR | |
| 65 | orr R1,R0,#0x80 @Disable IRQ interrupts | |
| 66 | msr CPSR_c,R1 | |
| 67 | tst R0,#0x80 | |
| 68 | moveq R0,#1 | |
| 69 | movne R0,#0 | |
| 70 | bx LR | |
| 71 | ||
| 72 | ASM_PFX(ArmGetInterruptState): | |
| 73 | mrs R0,CPSR | |
| 74 | tst R0,#0x80 @Check if IRQ is enabled. | |
| 75 | moveq R0,#1 | |
| 76 | movne R0,#0 | |
| 77 | bx LR | |
| 78 | ||
| 0416278c | 79 | ASM_PFX(ArmEnableFiq): |
| 80 | mrs R0,CPSR | |
| 81 | bic R0,R0,#0x40 @Enable FIQ interrupts | |
| 82 | msr CPSR_c,R0 | |
| 83 | bx LR | |
| 84 | ||
| 85 | ASM_PFX(ArmDisableFiq): | |
| 86 | mrs R0,CPSR | |
| 87 | orr R1,R0,#0x40 @Disable FIQ interrupts | |
| 88 | msr CPSR_c,R1 | |
| 89 | tst R0,#0x80 | |
| 90 | moveq R0,#1 | |
| 91 | movne R0,#0 | |
| 92 | bx LR | |
| 93 | ||
| 94 | ASM_PFX(ArmGetFiqState): | |
| 95 | mrs R0,CPSR | |
| 96 | tst R0,#0x80 @Check if FIQ is enabled. | |
| 97 | moveq R0,#1 | |
| 98 | movne R0,#0 | |
| 99 | bx LR | |
| 100 | ||
| 2ef2b01e A |
101 | ASM_PFX(ArmInvalidateTlb): |
| 102 | mov r0,#0 | |
| 103 | mcr p15,0,r0,c8,c7,0 | |
| 104 | bx lr | |
| 105 | ||
| 106 | ASM_PFX(ArmSetTranslationTableBaseAddress): | |
| 107 | mcr p15,0,r0,c2,c0,0 | |
| 108 | bx lr | |
| 109 | ||
| c2b5ca8b A |
110 | ASM_PFX(ArmGetTranslationTableBaseAddress): |
| 111 | mrc p15,0,r0,c2,c0,0 | |
| 112 | bx lr | |
| 113 | ||
| 114 | ||
| 2ef2b01e A |
115 | ASM_PFX(ArmSetDomainAccessControl): |
| 116 | mcr p15,0,r0,c3,c0,0 | |
| 117 | bx lr | |
| 118 | ||
| 119 | ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert | |
| 120 | stmfd sp!, {r4-r12, lr} @ save all the banked registers | |
| 121 | mov r3, sp @ copy the stack pointer into a non-banked register | |
| 122 | mrs r2, cpsr @ read the cpsr | |
| 123 | bic r2, r2, r0 @ clear mask in the cpsr | |
| 124 | and r1, r1, r0 @ clear bits outside the mask in the input | |
| 125 | orr r2, r2, r1 @ set field | |
| 126 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) | |
| 127 | mov sp, r3 @ restore stack pointer | |
| 128 | ldmfd sp!, {r4-r12, lr} @ restore registers | |
| 129 | bx lr @ return (hopefully thumb-safe!) | |
| 130 | ||
| 131 | ASM_PFX(CPSRRead): | |
| 132 | mrs r0, cpsr | |
| 133 | bx lr | |
| 134 | ||
| 135 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |