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1 | //------------------------------------------------------------------------------ |
2 | // | |
3 | // Copyright (c) 2008-2009 Apple Inc. All rights reserved. | |
4 | // | |
5 | // All rights reserved. This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | ||
16 | EXPORT Cp15IdCode | |
17 | EXPORT Cp15CacheInfo | |
18 | EXPORT ArmEnableInterrupts | |
19 | EXPORT ArmDisableInterrupts | |
20 | EXPORT ArmGetInterruptState | |
21 | EXPORT ArmInvalidateTlb | |
22 | EXPORT ArmSetTranslationTableBaseAddress | |
c2b5ca8b | 23 | EXPORT ArmGetTranslationTableBaseAddress |
2ef2b01e A |
24 | EXPORT ArmSetDomainAccessControl |
25 | EXPORT CPSRMaskInsert | |
26 | EXPORT CPSRRead | |
27 | ||
28 | AREA ArmLibSupport, CODE, READONLY | |
29 | ||
30 | Cp15IdCode | |
31 | mrc p15,0,R0,c0,c0,0 | |
32 | bx LR | |
33 | ||
34 | Cp15CacheInfo | |
35 | mrc p15,0,R0,c0,c0,1 | |
36 | bx LR | |
37 | ||
38 | ArmEnableInterrupts | |
39 | mrs R0,CPSR | |
40 | bic R0,R0,#0x80 ;Enable IRQ interrupts | |
41 | msr CPSR_c,R0 | |
42 | bx LR | |
43 | ||
44 | ArmDisableInterrupts | |
45 | mrs R0,CPSR | |
46 | orr R1,R0,#0x80 ;Disable IRQ interrupts | |
47 | msr CPSR_c,R1 | |
48 | tst R0,#0x80 | |
49 | moveq R0,#1 | |
50 | movne R0,#0 | |
51 | bx LR | |
52 | ||
53 | ArmGetInterruptState | |
54 | mrs R0,CPSR | |
55 | tst R0,#0x80 ;Check if IRQ is enabled. | |
56 | moveq R0,#1 | |
57 | movne R0,#0 | |
58 | bx LR | |
59 | ||
60 | ArmInvalidateTlb | |
61 | mov r0,#0 | |
62 | mcr p15,0,r0,c8,c7,0 | |
63 | bx lr | |
64 | ||
65 | ArmSetTranslationTableBaseAddress | |
66 | mcr p15,0,r0,c2,c0,0 | |
67 | bx lr | |
68 | ||
f659880b | 69 | ArmGetTranslationTableBaseAddress |
c2b5ca8b A |
70 | mrc p15,0,r0,c2,c0,0 |
71 | bx lr | |
72 | ||
2ef2b01e A |
73 | ArmSetDomainAccessControl |
74 | mcr p15,0,r0,c3,c0,0 | |
75 | bx lr | |
76 | ||
77 | CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert | |
78 | stmfd sp!, {r4-r12, lr} ; save all the banked registers | |
79 | mov r3, sp ; copy the stack pointer into a non-banked register | |
80 | mrs r2, cpsr ; read the cpsr | |
81 | bic r2, r2, r0 ; clear mask in the cpsr | |
82 | and r1, r1, r0 ; clear bits outside the mask in the input | |
83 | orr r2, r2, r1 ; set field | |
84 | msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) | |
85 | mov sp, r3 ; restore stack pointer | |
86 | ldmfd sp!, {r4-r12, lr} ; restore registers | |
87 | bx lr ; return (hopefully thumb-safe!) | |
88 | ||
89 | CPSRRead | |
90 | mrs r0, cpsr | |
91 | bx lr | |
92 | ||
93 | END | |
94 | ||
95 |