[mirror_edk2.git] / ArmPkg / Library / CompilerIntrinsicsLib / Arm / div.asm

//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
\r
    EXPORT  __aeabi_uidiv\r
    EXPORT  __aeabi_uidivmod\r
    EXPORT  __aeabi_idiv\r
    EXPORT  __aeabi_idivmod\r
    EXPORT  __rt_udiv\r
    EXPORT  __rt_sdiv\r
\r
    AREA  Math, CODE, READONLY\r
\r
;\r
;UINT32\r
;EFIAPI\r
;__aeabi_uidivmod (\r
;  IN UINT32  Dividend\r
;  IN UINT32  Divisor\r
;  );\r
;\r
__aeabi_uidiv\r
__aeabi_uidivmod\r
    RSBS    r12, r1, r0, LSR #4\r
    MOV     r2, #0\r
    BCC     __arm_div4\r
    RSBS    r12, r1, r0, LSR #8\r
    BCC     __arm_div8\r
    MOV     r3, #0\r
    B       __arm_div_large\r
\r
;\r
;UINT64\r
;EFIAPI\r
;__rt_udiv (\r
;  IN UINT32  Divisor,\r
;  IN UINT32  Dividend\r
;  );\r
;\r
__rt_udiv\r
    ; Swap R0 and R1\r
    MOV     r12, r0\r
    MOV     r0, r1\r
    MOV     r1, r12\r
    B       __aeabi_uidivmod\r
\r
;\r
;UINT64\r
;EFIAPI\r
;__rt_sdiv (\r
;  IN INT32  Divisor,\r
;  IN INT32  Dividend\r
;  );\r
;\r
__rt_sdiv\r
    ; Swap R0 and R1\r
    MOV     r12, r0\r
    MOV     r0, r1\r
    MOV     r1, r12\r
    B       __aeabi_idivmod\r
\r
;\r
;INT32\r
;EFIAPI\r
;__aeabi_idivmod (\r
;  IN INT32  Dividend\r
;  IN INT32  Divisor\r
;  );\r
;\r
__aeabi_idiv\r
__aeabi_idivmod\r
    ORRS    r12, r0, r1\r
    BMI     __arm_div_negative\r
    RSBS    r12, r1, r0, LSR #1\r
    MOV     r2, #0\r
    BCC     __arm_div1\r
    RSBS    r12, r1, r0, LSR #4\r
    BCC     __arm_div4\r
    RSBS    r12, r1, r0, LSR #8\r
    BCC     __arm_div8\r
    MOV     r3, #0\r
    B       __arm_div_large\r
__arm_div8\r
    RSBS    r12, r1, r0, LSR #7\r
    SUBCS   r0, r0, r1, LSL #7\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0,LSR #6\r
    SUBCS   r0, r0, r1, LSL #6\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #5\r
    SUBCS   r0, r0, r1, LSL #5\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #4\r
    SUBCS   r0, r0, r1, LSL #4\r
    ADC     r2, r2, r2\r
__arm_div4\r
    RSBS    r12, r1, r0, LSR #3\r
    SUBCS   r0, r0, r1, LSL #3\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #2\r
    SUBCS   r0, r0, r1, LSL #2\r
    ADCS    r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #1\r
    SUBCS   r0, r0, r1, LSL #1\r
    ADC     r2, r2, r2\r
__arm_div1\r
    SUBS    r1, r0, r1\r
    MOVCC   r1, r0\r
    ADC     r0, r2, r2\r
    BX      r14\r
__arm_div_negative\r
    ANDS    r2, r1, #0x80000000\r
    RSBMI   r1, r1, #0\r
    EORS    r3, r2, r0, ASR #32\r
    RSBCS   r0, r0, #0\r
    RSBS    r12, r1, r0, LSR #4\r
    BCC     label1\r
    RSBS    r12, r1, r0, LSR #8\r
    BCC     label2\r
__arm_div_large\r
    LSL     r1, r1, #6\r
    RSBS    r12, r1, r0, LSR #8\r
    ORR     r2, r2, #0xfc000000\r
    BCC     label2\r
    LSL     r1, r1, #6\r
    RSBS    r12, r1, r0, LSR #8\r
    ORR     r2, r2, #0x3f00000\r
    BCC     label2\r
    LSL     r1, r1, #6\r
    RSBS    r12, r1, r0, LSR #8\r
    ORR     r2, r2, #0xfc000\r
    ORRCS   r2, r2, #0x3f00\r
    LSLCS   r1, r1, #6\r
    RSBS    r12, r1, #0\r
    BCS     __aeabi_idiv0\r
label3\r
    LSRCS   r1, r1, #6\r
label2\r
    RSBS    r12, r1, r0, LSR #7\r
    SUBCS   r0, r0, r1, LSL #7\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #6\r
    SUBCS   r0, r0, r1, LSL #6\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #5\r
    SUBCS   r0, r0, r1, LSL #5\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #4\r
    SUBCS   r0, r0, r1, LSL #4\r
    ADC     r2, r2, r2\r
label1\r
    RSBS    r12, r1, r0, LSR #3\r
    SUBCS   r0, r0, r1, LSL #3\r
    ADC     r2, r2, r2\r
    RSBS    r12, r1, r0, LSR #2\r
    SUBCS   r0, r0, r1, LSL #2\r
    ADCS    r2, r2, r2\r
    BCS     label3\r
    RSBS    r12, r1, r0, LSR #1\r
    SUBCS   r0, r0, r1, LSL #1\r
    ADC     r2, r2, r2\r
    SUBS    r1, r0, r1\r
    MOVCC   r1, r0\r
    ADC     r0, r2, r2\r
    ASRS    r3, r3, #31\r
    RSBMI   r0, r0, #0\r
    RSBCS   r1, r1, #0\r
    BX      r14\r
\r
    ; What to do about division by zero?  For now, just return.\r
__aeabi_idiv0\r
    BX      r14\r
\r
    END\r
Commit	Line	Data
3402aac7	1	//------------------------------------------------------------------------------\r
1e57a462	2	//\r
1e57a462	3	// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
e58427e3	4	// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>\r
1e57a462	5	//\r
	6	// This program and the accompanying materials\r
	7	// are licensed and made available under the terms and conditions of the BSD License\r
	8	// which accompanies this distribution. The full text of the license may be found at\r
	9	// http://opensource.org/licenses/bsd-license.php\r
	10	//\r
	11	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	//\r
	14	//------------------------------------------------------------------------------\r
	15	\r
	16	\r
	17	EXPORT __aeabi_uidiv\r
	18	EXPORT __aeabi_uidivmod\r
	19	EXPORT __aeabi_idiv\r
	20	EXPORT __aeabi_idivmod\r
e58427e3 PB	21	EXPORT __rt_udiv\r
e58427e3 PB	22	EXPORT __rt_sdiv\r
3402aac7	23	\r
1e57a462	24	AREA Math, CODE, READONLY\r
	25	\r
	26	;\r
	27	;UINT32\r
	28	;EFIAPI\r
e58427e3 PB	29	;__aeabi_uidivmod (\r
e58427e3 PB	30	; IN UINT32 Dividend\r
1e57a462	31	; IN UINT32 Divisor\r
	32	; );\r
	33	;\r
1e57a462	34	__aeabi_uidiv\r
	35	__aeabi_uidivmod\r
	36	RSBS r12, r1, r0, LSR #4\r
	37	MOV r2, #0\r
	38	BCC __arm_div4\r
	39	RSBS r12, r1, r0, LSR #8\r
	40	BCC __arm_div8\r
	41	MOV r3, #0\r
	42	B __arm_div_large\r
	43	\r
e58427e3 PB	44	;\r
	45	;UINT64\r
	46	;EFIAPI\r
	47	;__rt_udiv (\r
	48	; IN UINT32 Divisor,\r
	49	; IN UINT32 Dividend\r
	50	; );\r
	51	;\r
	52	__rt_udiv\r
	53	; Swap R0 and R1\r
	54	MOV r12, r0\r
	55	MOV r0, r1\r
	56	MOV r1, r12\r
	57	B __aeabi_uidivmod\r
	58	\r
	59	;\r
	60	;UINT64\r
	61	;EFIAPI\r
	62	;__rt_sdiv (\r
	63	; IN INT32 Divisor,\r
	64	; IN INT32 Dividend\r
	65	; );\r
	66	;\r
	67	__rt_sdiv\r
	68	; Swap R0 and R1\r
	69	MOV r12, r0\r
	70	MOV r0, r1\r
	71	MOV r1, r12\r
	72	B __aeabi_idivmod\r
	73	\r
1e57a462	74	;\r
	75	;INT32\r
	76	;EFIAPI\r
e58427e3 PB	77	;__aeabi_idivmod (\r
e58427e3 PB	78	; IN INT32 Dividend\r
1e57a462	79	; IN INT32 Divisor\r
	80	; );\r
	81	;\r
	82	__aeabi_idiv\r
	83	__aeabi_idivmod\r
	84	ORRS r12, r0, r1\r
	85	BMI __arm_div_negative\r
	86	RSBS r12, r1, r0, LSR #1\r
	87	MOV r2, #0\r
	88	BCC __arm_div1\r
	89	RSBS r12, r1, r0, LSR #4\r
	90	BCC __arm_div4\r
	91	RSBS r12, r1, r0, LSR #8\r
	92	BCC __arm_div8\r
	93	MOV r3, #0\r
	94	B __arm_div_large\r
	95	__arm_div8\r
	96	RSBS r12, r1, r0, LSR #7\r
	97	SUBCS r0, r0, r1, LSL #7\r
	98	ADC r2, r2, r2\r
	99	RSBS r12, r1, r0,LSR #6\r
	100	SUBCS r0, r0, r1, LSL #6\r
	101	ADC r2, r2, r2\r
	102	RSBS r12, r1, r0, LSR #5\r
	103	SUBCS r0, r0, r1, LSL #5\r
	104	ADC r2, r2, r2\r
	105	RSBS r12, r1, r0, LSR #4\r
	106	SUBCS r0, r0, r1, LSL #4\r
	107	ADC r2, r2, r2\r
	108	__arm_div4\r
	109	RSBS r12, r1, r0, LSR #3\r
	110	SUBCS r0, r0, r1, LSL #3\r
	111	ADC r2, r2, r2\r
	112	RSBS r12, r1, r0, LSR #2\r
	113	SUBCS r0, r0, r1, LSL #2\r
	114	ADCS r2, r2, r2\r
	115	RSBS r12, r1, r0, LSR #1\r
	116	SUBCS r0, r0, r1, LSL #1\r
	117	ADC r2, r2, r2\r
	118	__arm_div1\r
	119	SUBS r1, r0, r1\r
	120	MOVCC r1, r0\r
	121	ADC r0, r2, r2\r
	122	BX r14\r
	123	__arm_div_negative\r
	124	ANDS r2, r1, #0x80000000\r
	125	RSBMI r1, r1, #0\r
	126	EORS r3, r2, r0, ASR #32\r
	127	RSBCS r0, r0, #0\r
	128	RSBS r12, r1, r0, LSR #4\r
	129	BCC label1\r
	130	RSBS r12, r1, r0, LSR #8\r
	131	BCC label2\r
	132	__arm_div_large\r
	133	LSL r1, r1, #6\r
	134	RSBS r12, r1, r0, LSR #8\r
	135	ORR r2, r2, #0xfc000000\r
	136	BCC label2\r
	137	LSL r1, r1, #6\r
	138	RSBS r12, r1, r0, LSR #8\r
	139	ORR r2, r2, #0x3f00000\r
	140	BCC label2\r
	141	LSL r1, r1, #6\r
	142	RSBS r12, r1, r0, LSR #8\r
143	ORR r2, r2, #0xfc000\r
144	ORRCS r2, r2, #0x3f00\r
145	LSLCS r1, r1, #6\r
146	RSBS r12, r1, #0\r
147	BCS __aeabi_idiv0\r
148	label3\r
149	LSRCS r1, r1, #6\r
150	label2\r
151	RSBS r12, r1, r0, LSR #7\r
152	SUBCS r0, r0, r1, LSL #7\r
153	ADC r2, r2, r2\r
154	RSBS r12, r1, r0, LSR #6\r
155	SUBCS r0, r0, r1, LSL #6\r
156	ADC r2, r2, r2\r
157	RSBS r12, r1, r0, LSR #5\r
158	SUBCS r0, r0, r1, LSL #5\r
159	ADC r2, r2, r2\r
160	RSBS r12, r1, r0, LSR #4\r
161	SUBCS r0, r0, r1, LSL #4\r
162	ADC r2, r2, r2\r
163	label1\r
164	RSBS r12, r1, r0, LSR #3\r
165	SUBCS r0, r0, r1, LSL #3\r
166	ADC r2, r2, r2\r
167	RSBS r12, r1, r0, LSR #2\r
168	SUBCS r0, r0, r1, LSL #2\r
169	ADCS r2, r2, r2\r
170	BCS label3\r
171	RSBS r12, r1, r0, LSR #1\r
172	SUBCS r0, r0, r1, LSL #1\r
173	ADC r2, r2, r2\r
174	SUBS r1, r0, r1\r
175	MOVCC r1, r0\r
176	ADC r0, r2, r2\r
177	ASRS r3, r3, #31\r
178	RSBMI r0, r0, #0\r
179	RSBCS r1, r1, #0\r
180	BX r14\r
181	\r
182	; What to do about division by zero? For now, just return.\r
183	__aeabi_idiv0\r
184	BX r14\r
3402aac7	185	\r
1e57a462	186	END\r