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1e57a462 | 1 | //------------------------------------------------------------------------------ \r |
2 | //\r | |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | //\r | |
5 | // This program and the accompanying materials\r | |
6 | // are licensed and made available under the terms and conditions of the BSD License\r | |
7 | // which accompanies this distribution. The full text of the license may be found at\r | |
8 | // http://opensource.org/licenses/bsd-license.php\r | |
9 | //\r | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | //\r | |
13 | //------------------------------------------------------------------------------\r | |
14 | \r | |
15 | \r | |
16 | \r | |
17 | .text\r | |
18 | .align 2\r | |
19 | GCC_ASM_EXPORT(__aeabi_uldivmod)\r | |
20 | \r | |
21 | // \r | |
22 | //UINT64\r | |
23 | //EFIAPI\r | |
24 | //__aeabi_uldivmod (\r | |
25 | // IN UINT64 Dividend \r | |
26 | // IN UINT64 Divisor\r | |
27 | // )\r | |
28 | //\r | |
29 | ASM_PFX(__aeabi_uldivmod):\r | |
30 | stmdb sp!, {r4, r5, r6, lr}\r | |
31 | mov r4, r1\r | |
32 | mov r5, r0\r | |
33 | mov r6, #0 // 0x0\r | |
34 | orrs ip, r3, r2, lsr #31\r | |
35 | bne ASM_PFX(__aeabi_uldivmod_label1)\r | |
36 | tst r2, r2\r | |
37 | beq ASM_PFX(_ll_div0)\r | |
38 | movs ip, r2, lsr #15\r | |
39 | addeq r6, r6, #16 // 0x10\r | |
40 | mov ip, r2, lsl r6\r | |
41 | movs lr, ip, lsr #23\r | |
42 | moveq ip, ip, lsl #8\r | |
43 | addeq r6, r6, #8 // 0x8\r | |
44 | movs lr, ip, lsr #27\r | |
45 | moveq ip, ip, lsl #4\r | |
46 | addeq r6, r6, #4 // 0x4\r | |
47 | movs lr, ip, lsr #29\r | |
48 | moveq ip, ip, lsl #2\r | |
49 | addeq r6, r6, #2 // 0x2\r | |
50 | movs lr, ip, lsr #30\r | |
51 | moveq ip, ip, lsl #1\r | |
52 | addeq r6, r6, #1 // 0x1\r | |
53 | b ASM_PFX(_ll_udiv_small)\r | |
54 | ASM_PFX(__aeabi_uldivmod_label1):\r | |
55 | tst r3, #-2147483648 // 0x80000000\r | |
56 | bne ASM_PFX(__aeabi_uldivmod_label2)\r | |
57 | movs ip, r3, lsr #15\r | |
58 | addeq r6, r6, #16 // 0x10\r | |
59 | mov ip, r3, lsl r6\r | |
60 | movs lr, ip, lsr #23\r | |
61 | moveq ip, ip, lsl #8\r | |
62 | addeq r6, r6, #8 // 0x8\r | |
63 | movs lr, ip, lsr #27\r | |
64 | moveq ip, ip, lsl #4\r | |
65 | addeq r6, r6, #4 // 0x4\r | |
66 | movs lr, ip, lsr #29\r | |
67 | moveq ip, ip, lsl #2\r | |
68 | addeq r6, r6, #2 // 0x2\r | |
69 | movs lr, ip, lsr #30\r | |
70 | addeq r6, r6, #1 // 0x1\r | |
71 | rsb r3, r6, #32 // 0x20\r | |
72 | moveq ip, ip, lsl #1\r | |
73 | orr ip, ip, r2, lsr r3\r | |
74 | mov lr, r2, lsl r6\r | |
75 | b ASM_PFX(_ll_udiv_big)\r | |
76 | ASM_PFX(__aeabi_uldivmod_label2):\r | |
77 | mov ip, r3\r | |
78 | mov lr, r2\r | |
79 | b ASM_PFX(_ll_udiv_ginormous)\r | |
80 | \r | |
81 | ASM_PFX(_ll_udiv_small):\r | |
82 | cmp r4, ip, lsl #1\r | |
83 | mov r3, #0 // 0x0\r | |
84 | subcs r4, r4, ip, lsl #1\r | |
85 | addcs r3, r3, #2 // 0x2\r | |
86 | cmp r4, ip\r | |
87 | subcs r4, r4, ip\r | |
88 | adcs r3, r3, #0 // 0x0\r | |
89 | add r2, r6, #32 // 0x20\r | |
90 | cmp r2, #32 // 0x20\r | |
91 | rsb ip, ip, #0 // 0x0\r | |
92 | bcc ASM_PFX(_ll_udiv_small_label1)\r | |
93 | orrs r0, r4, r5, lsr #30\r | |
94 | moveq r4, r5\r | |
95 | moveq r5, #0 // 0x0\r | |
96 | subeq r2, r2, #32 // 0x20\r | |
97 | ASM_PFX(_ll_udiv_small_label1):\r | |
98 | mov r1, #0 // 0x0\r | |
99 | cmp r2, #16 // 0x10\r | |
100 | bcc ASM_PFX(_ll_udiv_small_label2)\r | |
101 | movs r0, r4, lsr #14\r | |
102 | moveq r4, r4, lsl #16\r | |
103 | addeq r1, r1, #16 // 0x10\r | |
104 | ASM_PFX(_ll_udiv_small_label2):\r | |
105 | sub lr, r2, r1\r | |
106 | cmp lr, #8 // 0x8\r | |
107 | bcc ASM_PFX(_ll_udiv_small_label3)\r | |
108 | movs r0, r4, lsr #22\r | |
109 | moveq r4, r4, lsl #8\r | |
110 | addeq r1, r1, #8 // 0x8\r | |
111 | ASM_PFX(_ll_udiv_small_label3):\r | |
112 | rsb r0, r1, #32 // 0x20\r | |
113 | sub r2, r2, r1\r | |
114 | orr r4, r4, r5, lsr r0\r | |
115 | mov r5, r5, lsl r1\r | |
116 | cmp r2, #1 // 0x1\r | |
117 | bcc ASM_PFX(_ll_udiv_small_label5)\r | |
118 | sub r2, r2, #1 // 0x1\r | |
119 | and r0, r2, #7 // 0x7\r | |
120 | eor r0, r0, #7 // 0x7\r | |
121 | adds r0, r0, r0, lsl #1\r | |
122 | add pc, pc, r0, lsl #2\r | |
123 | nop // (mov r0,r0)\r | |
124 | ASM_PFX(_ll_udiv_small_label4):\r | |
125 | adcs r5, r5, r5\r | |
126 | adcs r4, ip, r4, lsl #1\r | |
127 | rsbcc r4, ip, r4\r | |
128 | adcs r5, r5, r5\r | |
129 | adcs r4, ip, r4, lsl #1\r | |
130 | rsbcc r4, ip, r4\r | |
131 | adcs r5, r5, r5\r | |
132 | adcs r4, ip, r4, lsl #1\r | |
133 | rsbcc r4, ip, r4\r | |
134 | adcs r5, r5, r5\r | |
135 | adcs r4, ip, r4, lsl #1\r | |
136 | rsbcc r4, ip, r4\r | |
137 | adcs r5, r5, r5\r | |
138 | adcs r4, ip, r4, lsl #1\r | |
139 | rsbcc r4, ip, r4\r | |
140 | adcs r5, r5, r5\r | |
141 | adcs r4, ip, r4, lsl #1\r | |
142 | rsbcc r4, ip, r4\r | |
143 | adcs r5, r5, r5\r | |
144 | adcs r4, ip, r4, lsl #1\r | |
145 | rsbcc r4, ip, r4\r | |
146 | adcs r5, r5, r5\r | |
147 | adcs r4, ip, r4, lsl #1\r | |
148 | sub r2, r2, #8 // 0x8\r | |
149 | tst r2, r2\r | |
150 | rsbcc r4, ip, r4\r | |
151 | bpl ASM_PFX(_ll_udiv_small_label4)\r | |
152 | ASM_PFX(_ll_udiv_small_label5):\r | |
153 | mov r2, r4, lsr r6\r | |
154 | bic r4, r4, r2, lsl r6\r | |
155 | adcs r0, r5, r5\r | |
156 | adc r1, r4, r4\r | |
157 | add r1, r1, r3, lsl r6\r | |
158 | mov r3, #0 // 0x0\r | |
159 | ldmia sp!, {r4, r5, r6, pc}\r | |
160 | \r | |
161 | ASM_PFX(_ll_udiv_big):\r | |
162 | subs r0, r5, lr\r | |
163 | mov r3, #0 // 0x0\r | |
164 | sbcs r1, r4, ip\r | |
165 | movcs r5, r0\r | |
166 | movcs r4, r1\r | |
167 | adcs r3, r3, #0 // 0x0\r | |
168 | subs r0, r5, lr\r | |
169 | sbcs r1, r4, ip\r | |
170 | movcs r5, r0\r | |
171 | movcs r4, r1\r | |
172 | adcs r3, r3, #0 // 0x0\r | |
173 | subs r0, r5, lr\r | |
174 | sbcs r1, r4, ip\r | |
175 | movcs r5, r0\r | |
176 | movcs r4, r1\r | |
177 | adcs r3, r3, #0 // 0x0\r | |
178 | mov r1, #0 // 0x0\r | |
179 | rsbs lr, lr, #0 // 0x0\r | |
180 | rsc ip, ip, #0 // 0x0\r | |
181 | cmp r6, #16 // 0x10\r | |
182 | bcc ASM_PFX(_ll_udiv_big_label1)\r | |
183 | movs r0, r4, lsr #14\r | |
184 | moveq r4, r4, lsl #16\r | |
185 | addeq r1, r1, #16 // 0x10\r | |
186 | ASM_PFX(_ll_udiv_big_label1):\r | |
187 | sub r2, r6, r1\r | |
188 | cmp r2, #8 // 0x8\r | |
189 | bcc ASM_PFX(_ll_udiv_big_label2)\r | |
190 | movs r0, r4, lsr #22\r | |
191 | moveq r4, r4, lsl #8\r | |
192 | addeq r1, r1, #8 // 0x8\r | |
193 | ASM_PFX(_ll_udiv_big_label2):\r | |
194 | rsb r0, r1, #32 // 0x20\r | |
195 | sub r2, r6, r1\r | |
196 | orr r4, r4, r5, lsr r0\r | |
197 | mov r5, r5, lsl r1\r | |
198 | cmp r2, #1 // 0x1\r | |
199 | bcc ASM_PFX(_ll_udiv_big_label4)\r | |
200 | sub r2, r2, #1 // 0x1\r | |
201 | and r0, r2, #3 // 0x3\r | |
202 | rsb r0, r0, #3 // 0x3\r | |
203 | adds r0, r0, r0, lsl #1\r | |
204 | add pc, pc, r0, lsl #3\r | |
205 | nop // (mov r0,r0)\r | |
206 | ASM_PFX(_ll_udiv_big_label3):\r | |
207 | adcs r5, r5, r5\r | |
208 | adcs r4, r4, r4\r | |
209 | adcs r0, lr, r5\r | |
210 | adcs r1, ip, r4\r | |
211 | movcs r5, r0\r | |
212 | movcs r4, r1\r | |
213 | adcs r5, r5, r5\r | |
214 | adcs r4, r4, r4\r | |
215 | adcs r0, lr, r5\r | |
216 | adcs r1, ip, r4\r | |
217 | movcs r5, r0\r | |
218 | movcs r4, r1\r | |
219 | adcs r5, r5, r5\r | |
220 | adcs r4, r4, r4\r | |
221 | adcs r0, lr, r5\r | |
222 | adcs r1, ip, r4\r | |
223 | movcs r5, r0\r | |
224 | movcs r4, r1\r | |
225 | sub r2, r2, #4 // 0x4\r | |
226 | adcs r5, r5, r5\r | |
227 | adcs r4, r4, r4\r | |
228 | adcs r0, lr, r5\r | |
229 | adcs r1, ip, r4\r | |
230 | tst r2, r2\r | |
231 | movcs r5, r0\r | |
232 | movcs r4, r1\r | |
233 | bpl ASM_PFX(_ll_udiv_big_label3)\r | |
234 | ASM_PFX(_ll_udiv_big_label4):\r | |
235 | mov r1, #0 // 0x0\r | |
236 | mov r2, r5, lsr r6\r | |
237 | bic r5, r5, r2, lsl r6\r | |
238 | adcs r0, r5, r5\r | |
239 | adc r1, r1, #0 // 0x0\r | |
240 | movs lr, r3, lsl r6\r | |
241 | mov r3, r4, lsr r6\r | |
242 | bic r4, r4, r3, lsl r6\r | |
243 | adc r1, r1, #0 // 0x0\r | |
244 | adds r0, r0, lr\r | |
245 | orr r2, r2, r4, ror r6\r | |
246 | adc r1, r1, #0 // 0x0\r | |
247 | ldmia sp!, {r4, r5, r6, pc}\r | |
248 | \r | |
249 | ASM_PFX(_ll_udiv_ginormous):\r | |
250 | subs r2, r5, lr\r | |
251 | mov r1, #0 // 0x0\r | |
252 | sbcs r3, r4, ip\r | |
253 | adc r0, r1, r1\r | |
254 | movcc r2, r5\r | |
255 | movcc r3, r4\r | |
256 | ldmia sp!, {r4, r5, r6, pc}\r | |
257 | \r | |
258 | ASM_PFX(_ll_div0):\r | |
259 | ldmia sp!, {r4, r5, r6, lr}\r | |
260 | mov r0, #0 // 0x0\r | |
261 | mov r1, #0 // 0x0\r | |
262 | b ASM_PFX(__aeabi_ldiv0)\r | |
263 | \r | |
264 | ASM_PFX(__aeabi_ldiv0):\r | |
265 | bx r14\r | |
266 | \r | |
267 | \r |