]> git.proxmox.com Git - mirror_edk2.git/blame - ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
ArmPkg: Apply uncrustify changes
[mirror_edk2.git] / ArmPkg / Universal / Smbios / ProcessorSubClassDxe / SmbiosProcessorAArch64.c
CommitLineData
2ba6ecef
RC
1/** @file\r
2 Functions for AARCH64 processor information\r
3\r
4 Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
5\r
6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
7\r
8**/\r
9\r
10#include <Uefi.h>\r
a63914d3 11#include <IndustryStandard/ArmCache.h>\r
2ba6ecef 12#include <Library/ArmLib.h>\r
2ba6ecef
RC
13\r
14#include "SmbiosProcessor.h"\r
15\r
16/** Gets the size of the specified cache.\r
17\r
18 @param CacheLevel The cache level (L1, L2 etc.).\r
19 @param DataCache Whether the cache is a dedicated data cache.\r
20 @param UnifiedCache Whether the cache is a unified cache.\r
21\r
22 @return The cache size.\r
23**/\r
24UINT64\r
25SmbiosProcessorGetCacheSize (\r
429309e0
MK
26 IN UINT8 CacheLevel,\r
27 IN BOOLEAN DataCache,\r
28 IN BOOLEAN UnifiedCache\r
29 )\r
2ba6ecef 30{\r
429309e0
MK
31 CCSIDR_DATA Ccsidr;\r
32 CSSELR_DATA Csselr;\r
33 BOOLEAN CcidxSupported;\r
34 UINT64 CacheSize;\r
2ba6ecef 35\r
429309e0 36 Csselr.Data = 0;\r
2ba6ecef 37 Csselr.Bits.Level = CacheLevel - 1;\r
429309e0 38 Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
2ba6ecef
RC
39\r
40 Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
41\r
42 CcidxSupported = ArmHasCcidx ();\r
43\r
44 if (CcidxSupported) {\r
45 CacheSize = (1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) *\r
429309e0
MK
46 (Ccsidr.BitsCcidxAA64.Associativity + 1) *\r
47 (Ccsidr.BitsCcidxAA64.NumSets + 1);\r
2ba6ecef
RC
48 } else {\r
49 CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *\r
429309e0
MK
50 (Ccsidr.BitsNonCcidx.Associativity + 1) *\r
51 (Ccsidr.BitsNonCcidx.NumSets + 1);\r
2ba6ecef
RC
52 }\r
53\r
54 return CacheSize;\r
55}\r
56\r
57/** Gets the associativity of the specified cache.\r
58\r
59 @param CacheLevel The cache level (L1, L2 etc.).\r
60 @param DataCache Whether the cache is a dedicated data cache.\r
61 @param UnifiedCache Whether the cache is a unified cache.\r
62\r
63 @return The cache associativity.\r
64**/\r
65UINT32\r
66SmbiosProcessorGetCacheAssociativity (\r
429309e0
MK
67 IN UINT8 CacheLevel,\r
68 IN BOOLEAN DataCache,\r
69 IN BOOLEAN UnifiedCache\r
2ba6ecef
RC
70 )\r
71{\r
429309e0
MK
72 CCSIDR_DATA Ccsidr;\r
73 CSSELR_DATA Csselr;\r
74 BOOLEAN CcidxSupported;\r
75 UINT32 Associativity;\r
2ba6ecef 76\r
429309e0 77 Csselr.Data = 0;\r
2ba6ecef 78 Csselr.Bits.Level = CacheLevel - 1;\r
429309e0 79 Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r
2ba6ecef
RC
80\r
81 Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r
82\r
83 CcidxSupported = ArmHasCcidx ();\r
84\r
85 if (CcidxSupported) {\r
86 Associativity = Ccsidr.BitsCcidxAA64.Associativity + 1;\r
87 } else {\r
88 Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;\r
89 }\r
90\r
91 return Associativity;\r
92}\r