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1 | /** @file\r |
2 | Functions for ARM processor information\r | |
3 | \r | |
4 | Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | \r | |
10 | #include <Uefi.h>\r | |
a63914d3 | 11 | #include <IndustryStandard/ArmCache.h>\r |
2ba6ecef | 12 | #include <Library/ArmLib.h>\r |
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13 | \r |
14 | #include "SmbiosProcessor.h"\r | |
15 | \r | |
16 | /** Gets the size of the specified cache.\r | |
17 | \r | |
18 | @param CacheLevel The cache level (L1, L2 etc.).\r | |
19 | @param DataCache Whether the cache is a dedicated data cache.\r | |
20 | @param UnifiedCache Whether the cache is a unified cache.\r | |
21 | \r | |
22 | @return The cache size.\r | |
23 | **/\r | |
24 | UINT64\r | |
c615265b | 25 | SmbiosProcessorGetCacheSize (\r |
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26 | IN UINT8 CacheLevel,\r |
27 | IN BOOLEAN DataCache,\r | |
28 | IN BOOLEAN UnifiedCache\r | |
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29 | )\r |
30 | {\r | |
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31 | CCSIDR_DATA Ccsidr;\r |
32 | CCSIDR2_DATA Ccsidr2;\r | |
33 | CSSELR_DATA Csselr;\r | |
34 | BOOLEAN CcidxSupported;\r | |
35 | UINT64 CacheSize;\r | |
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36 | \r |
37 | // Read the CCSIDR register to get the cache architecture\r | |
429309e0 | 38 | Csselr.Data = 0;\r |
2ba6ecef | 39 | Csselr.Bits.Level = CacheLevel - 1;\r |
429309e0 | 40 | Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r |
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41 | \r |
42 | Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r | |
43 | \r | |
44 | CcidxSupported = ArmHasCcidx ();\r | |
45 | \r | |
46 | if (CcidxSupported) {\r | |
47 | Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);\r | |
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48 | CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *\r |
49 | (Ccsidr.BitsCcidxAA32.Associativity + 1) *\r | |
50 | (Ccsidr2.Bits.NumSets + 1);\r | |
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51 | } else {\r |
52 | CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *\r | |
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53 | (Ccsidr.BitsNonCcidx.Associativity + 1) *\r |
54 | (Ccsidr.BitsNonCcidx.NumSets + 1);\r | |
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55 | }\r |
56 | \r | |
57 | return CacheSize;\r | |
58 | }\r | |
59 | \r | |
60 | /** Gets the associativity of the specified cache.\r | |
61 | \r | |
62 | @param CacheLevel The cache level (L1, L2 etc.).\r | |
63 | @param DataCache Whether the cache is a dedicated data cache.\r | |
64 | @param UnifiedCache Whether the cache is a unified cache.\r | |
65 | \r | |
66 | @return The cache associativity.\r | |
67 | **/\r | |
68 | UINT32\r | |
c615265b | 69 | SmbiosProcessorGetCacheAssociativity (\r |
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70 | IN UINT8 CacheLevel,\r |
71 | IN BOOLEAN DataCache,\r | |
72 | IN BOOLEAN UnifiedCache\r | |
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73 | )\r |
74 | {\r | |
75 | CCSIDR_DATA Ccsidr;\r | |
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76 | CSSELR_DATA Csselr;\r |
77 | BOOLEAN CcidxSupported;\r | |
78 | UINT32 Associativity;\r | |
79 | \r | |
80 | // Read the CCSIDR register to get the cache architecture\r | |
429309e0 | 81 | Csselr.Data = 0;\r |
2ba6ecef | 82 | Csselr.Bits.Level = CacheLevel - 1;\r |
429309e0 | 83 | Csselr.Bits.InD = (!DataCache && !UnifiedCache);\r |
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84 | \r |
85 | Ccsidr.Data = ReadCCSIDR (Csselr.Data);\r | |
86 | \r | |
87 | CcidxSupported = ArmHasCcidx ();\r | |
88 | \r | |
89 | if (CcidxSupported) {\r | |
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90 | Associativity = Ccsidr.BitsCcidxAA32.Associativity + 1;\r |
91 | } else {\r | |
92 | Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;\r | |
93 | }\r | |
94 | \r | |
95 | return Associativity;\r | |
96 | }\r |