ArmPkg: Apply uncrustify changes

[mirror_edk2.git] / ArmPkg / Universal / Smbios / ProcessorSubClassDxe / SmbiosProcessorArmCommon.c

/** @file\r
  Functions for processor information common to ARM and AARCH64.\r
\r
  Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
  Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Uefi.h>\r
#include <IndustryStandard/ArmCache.h>\r
#include <IndustryStandard/ArmStdSmc.h>\r
#include <IndustryStandard/SmBios.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmSmcLib.h>\r
#include <Library/BaseMemoryLib.h>\r
\r
#include "SmbiosProcessor.h"\r
\r
/** Returns the maximum cache level implemented by the current CPU.\r
\r
    @return The maximum cache level implemented.\r
**/\r
UINT8\r
SmbiosProcessorGetMaxCacheLevel (\r
  VOID\r
  )\r
{\r
  CLIDR_DATA  Clidr;\r
  UINT8       CacheLevel;\r
  UINT8       MaxCacheLevel;\r
\r
  MaxCacheLevel = 0;\r
\r
  // Read the CLIDR register to find out what caches are present.\r
  Clidr.Data = ReadCLIDR ();\r
\r
  // Get the cache type for the L1 cache. If it's 0, there are no caches.\r
  if (CLIDR_GET_CACHE_TYPE (Clidr.Data, 1) == ClidrCacheTypeNone) {\r
    return 0;\r
  }\r
\r
  for (CacheLevel = 1; CacheLevel <= MAX_ARM_CACHE_LEVEL; CacheLevel++) {\r
    if (CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel) == ClidrCacheTypeNone) {\r
      MaxCacheLevel = CacheLevel;\r
      break;\r
    }\r
  }\r
\r
  return MaxCacheLevel;\r
}\r
\r
/** Returns whether or not the specified cache level has separate I/D caches.\r
\r
    @param CacheLevel The cache level (L1, L2 etc.).\r
\r
    @return TRUE if the cache level has separate I/D caches, FALSE otherwise.\r
**/\r
BOOLEAN\r
SmbiosProcessorHasSeparateCaches (\r
  UINT8  CacheLevel\r
  )\r
{\r
  CLIDR_CACHE_TYPE  CacheType;\r
  CLIDR_DATA        Clidr;\r
  BOOLEAN           SeparateCaches;\r
\r
  SeparateCaches = FALSE;\r
\r
  Clidr.Data = ReadCLIDR ();\r
\r
  CacheType = CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel - 1);\r
\r
  if (CacheType == ClidrCacheTypeSeparate) {\r
    SeparateCaches = TRUE;\r
  }\r
\r
  return SeparateCaches;\r
}\r
\r
/** Checks if ther ARM64 SoC ID SMC call is supported\r
\r
    @return Whether the ARM64 SoC ID call is supported.\r
**/\r
BOOLEAN\r
HasSmcArm64SocId (\r
  VOID\r
  )\r
{\r
  ARM_SMC_ARGS  Args;\r
  INT32         SmcCallStatus;\r
  BOOLEAN       Arm64SocIdSupported;\r
\r
  Arm64SocIdSupported = FALSE;\r
\r
  Args.Arg0 = SMCCC_VERSION;\r
  ArmCallSmc (&Args);\r
  SmcCallStatus = (INT32)Args.Arg0;\r
\r
  if ((SmcCallStatus < 0) || ((SmcCallStatus >> 16) >= 1)) {\r
    Args.Arg0 = SMCCC_ARCH_FEATURES;\r
    Args.Arg1 = SMCCC_ARCH_SOC_ID;\r
    ArmCallSmc (&Args);\r
\r
    if (Args.Arg0 >= 0) {\r
      Arm64SocIdSupported = TRUE;\r
    }\r
  }\r
\r
  return Arm64SocIdSupported;\r
}\r
\r
/** Fetches the JEP106 code and SoC Revision.\r
\r
    @param Jep106Code  JEP 106 code.\r
    @param SocRevision SoC revision.\r
\r
    @retval EFI_SUCCESS Succeeded.\r
    @retval EFI_UNSUPPORTED Failed.\r
**/\r
EFI_STATUS\r
SmbiosGetSmcArm64SocId (\r
  OUT INT32  *Jep106Code,\r
  OUT INT32  *SocRevision\r
  )\r
{\r
  ARM_SMC_ARGS  Args;\r
  INT32         SmcCallStatus;\r
  EFI_STATUS    Status;\r
\r
  Status = EFI_SUCCESS;\r
\r
  Args.Arg0 = SMCCC_ARCH_SOC_ID;\r
  Args.Arg1 = 0;\r
  ArmCallSmc (&Args);\r
  SmcCallStatus = (INT32)Args.Arg0;\r
\r
  if (SmcCallStatus >= 0) {\r
    *Jep106Code = (INT32)Args.Arg0;\r
  } else {\r
    Status = EFI_UNSUPPORTED;\r
  }\r
\r
  Args.Arg0 = SMCCC_ARCH_SOC_ID;\r
  Args.Arg1 = 1;\r
  ArmCallSmc (&Args);\r
  SmcCallStatus = (INT32)Args.Arg0;\r
\r
  if (SmcCallStatus >= 0) {\r
    *SocRevision = (INT32)Args.Arg0;\r
  } else {\r
    Status = EFI_UNSUPPORTED;\r
  }\r
\r
  return Status;\r
}\r
\r
/** Returns a value for the Processor ID field that conforms to SMBIOS\r
    requirements.\r
\r
    @return Processor ID.\r
**/\r
UINT64\r
SmbiosGetProcessorId (\r
  VOID\r
  )\r
{\r
  INT32   Jep106Code;\r
  INT32   SocRevision;\r
  UINT64  ProcessorId;\r
\r
  if (HasSmcArm64SocId ()) {\r
    SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);\r
    ProcessorId = ((UINT64)SocRevision << 32) | Jep106Code;\r
  } else {\r
    ProcessorId = ArmReadMidr ();\r
  }\r
\r
  return ProcessorId;\r
}\r
\r
/** Returns the external clock frequency.\r
\r
    @return The external clock frequency.\r
**/\r
UINTN\r
SmbiosGetExternalClockFrequency (\r
  VOID\r
  )\r
{\r
  return ArmReadCntFrq ();\r
}\r
\r
/** Returns the SMBIOS ProcessorFamily field value.\r
\r
    @return The value for the ProcessorFamily field.\r
**/\r
UINT8\r
SmbiosGetProcessorFamily (\r
  VOID\r
  )\r
{\r
  return ProcessorFamilyIndicatorFamily2;\r
}\r
\r
/** Returns the ProcessorFamily2 field value.\r
\r
    @return The value for the ProcessorFamily2 field.\r
**/\r
UINT16\r
SmbiosGetProcessorFamily2 (\r
  VOID\r
  )\r
{\r
  UINTN   MainIdRegister;\r
  UINT16  ProcessorFamily2;\r
\r
  MainIdRegister = ArmReadMidr ();\r
\r
  if (((MainIdRegister >> 16) & 0xF) < 8) {\r
    ProcessorFamily2 = ProcessorFamilyARM;\r
  } else {\r
    if (sizeof (VOID *) == 4) {\r
      ProcessorFamily2 = ProcessorFamilyARMv7;\r
    } else {\r
      ProcessorFamily2 = ProcessorFamilyARMv8;\r
    }\r
  }\r
\r
  return ProcessorFamily2;\r
}\r
\r
/** Returns the SMBIOS Processor Characteristics.\r
\r
    @return Processor Characteristics bitfield.\r
**/\r
PROCESSOR_CHARACTERISTIC_FLAGS\r
SmbiosGetProcessorCharacteristics (\r
  VOID\r
  )\r
{\r
  PROCESSOR_CHARACTERISTIC_FLAGS  Characteristics;\r
\r
  ZeroMem (&Characteristics, sizeof (Characteristics));\r
\r
  Characteristics.ProcessorArm64SocId = HasSmcArm64SocId ();\r
\r
  return Characteristics;\r
}\r