[mirror_edk2.git] / ArmPlatformPkg / ArmJunoPkg / Drivers / PciHostBridgeDxe / PciRootBridge.c

/** @file\r
*  Implementation of the PCI Root Bridge Protocol for XPress-RICH3 PCIe Root Complex\r
*\r
*  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include "PciHostBridge.h"\r
\r
#include <Library/DevicePathLib.h>\r
#include <Library/DmaLib.h>\r
\r
#define CPUIO_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridge->CpuIo)\r
#define METRONOME_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridge->Metronome)\r
\r
/**\r
 * PCI Root Bridge Instance Templates\r
 */\r
STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH  gDevicePathTemplate = {\r
    {\r
      { ACPI_DEVICE_PATH,\r
        ACPI_DP,\r
        { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\r
          (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) }\r
      },\r
      EISA_PNP_ID (0x0A03),\r
      0\r
    },\r
    {\r
      END_DEVICE_PATH_TYPE,\r
      END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
      { END_DEVICE_PATH_LENGTH, 0 }\r
    }\r
};\r
\r
STATIC CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL gIoTemplate = {\r
    0,\r
    PciRbPollMem,\r
    PciRbPollIo,\r
    {\r
      PciRbMemRead,\r
      PciRbMemWrite\r
    },\r
    {\r
      PciRbIoRead,\r
      PciRbIoWrite\r
    },\r
    {\r
      PciRbPciRead,\r
      PciRbPciWrite\r
    },\r
    PciRbCopyMem,\r
    PciRbMap,\r
    PciRbUnMap,\r
    PciRbAllocateBuffer,\r
    PciRbFreeBuffer,\r
    PciRbFlush,\r
    PciRbGetAttributes,\r
    PciRbSetAttributes,\r
    PciRbConfiguration,\r
    0\r
  };\r
\r
typedef struct {\r
    EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     SpaceDesp[ResTypeMax+1];\r
    EFI_ACPI_END_TAG_DESCRIPTOR           EndDesp;\r
} RESOURCE_CONFIGURATION;\r
\r
\r
RESOURCE_CONFIGURATION Configuration = {\r
   {{ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_IO , 0, 0, 0, 0, 0, 0, 0},\r
    {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 0, 32, 0, 0, 0, 0},\r
    {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 6, 32, 0, 0, 0, 0},\r
    {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 0, 64, 0, 0, 0, 0},\r
    {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 6, 64, 0, 0, 0, 0},\r
    {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_BUS, 0, 0, 0, 0, 255, 0, 255}},\r
    {ACPI_END_TAG_DESCRIPTOR, 0}\r
};\r
\r
\r
EFI_STATUS\r
PciRbPollMem (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT64                                   Address,\r
  IN  UINT64                                   Mask,\r
  IN  UINT64                                   Value,\r
  IN  UINT64                                   Delay,\r
  OUT UINT64                                   *Result\r
  )\r
{\r
  EFI_STATUS                      Status;\r
  UINT64                          NumberOfTicks;\r
  UINT32                          Remainder;\r
  PCI_ROOT_BRIDGE_INSTANCE        *RootBridgeInstance;\r
  EFI_METRONOME_ARCH_PROTOCOL     *Metronome;\r
\r
  PCI_TRACE ("PciRbPollMem()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  Metronome = METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  // No matter what, always do a single poll.\r
  Status = This->Mem.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) Metronome->TickPeriod, &Remainder);\r
  if (Remainder != 0) {\r
    NumberOfTicks += 1;\r
  }\r
  NumberOfTicks += 1;\r
\r
  while (NumberOfTicks) {\r
    Metronome->WaitForTick (Metronome, 1);\r
\r
    Status = This->Mem.Read (This, Width, Address, 1, Result);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
    if ((*Result & Mask) == Value) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    NumberOfTicks -= 1;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
EFI_STATUS\r
PciRbPollIo (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT64                                   Address,\r
  IN  UINT64                                   Mask,\r
  IN  UINT64                                   Value,\r
  IN  UINT64                                   Delay,\r
  OUT UINT64                                   *Result\r
  )\r
{\r
  EFI_STATUS                      Status;\r
  UINT64                          NumberOfTicks;\r
  UINT32                          Remainder;\r
  PCI_ROOT_BRIDGE_INSTANCE        *RootBridgeInstance;\r
  EFI_METRONOME_ARCH_PROTOCOL     *Metronome;\r
\r
  PCI_TRACE ("PciRbPollIo()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  Metronome = METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  // No matter what, always do a single poll.\r
  Status = This->Io.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) Metronome->TickPeriod, &Remainder);\r
  if (Remainder != 0) {\r
    NumberOfTicks += 1;\r
  }\r
  NumberOfTicks += 1;\r
\r
  while (NumberOfTicks) {\r
    Metronome->WaitForTick (Metronome, 1);\r
\r
    Status = This->Io.Read (This, Width, Address, 1, Result);\r
    if (EFI_ERROR (Status)) {\r
        return Status;\r
    }\r
\r
    if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
    }\r
\r
    NumberOfTicks -= 1;\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
EFI_STATUS\r
PciRbMemRead (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
  EFI_CPU_IO2_PROTOCOL        *CpuIo;\r
\r
  PCI_TRACE ("PciRbMemRead()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM32_SIZE))) &&\r
      ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM64_SIZE)))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
PciRbMemWrite (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
  EFI_CPU_IO2_PROTOCOL        *CpuIo;\r
\r
  PCI_TRACE ("PciRbMemWrite()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM32_SIZE))) &&\r
      ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM64_SIZE)))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
PciRbIoRead (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  PCI_TRACE ("PciRbIoRead()");\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  // IO currently unsupported\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
EFI_STATUS\r
PciRbIoWrite (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  PCI_TRACE ("PciRbIoWrite()");\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  // IO currently unsupported\r
  return EFI_INVALID_PARAMETER;\r
}\r
\r
EFI_STATUS\r
PciRbPciRead (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   EfiAddress,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  UINT32                      Offset;\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
  EFI_CPU_IO2_PROTOCOL        *CpuIo;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;\r
  UINT64                      Address;\r
\r
  EfiPciAddress  = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (EfiPciAddress->ExtendedRegister) {\r
    Offset = EfiPciAddress->ExtendedRegister;\r
  } else {\r
    Offset = EfiPciAddress->Register;\r
  }\r
\r
  // The UEFI PCI enumerator scans for devices at all possible addresses,\r
  // and ignores some PCI rules - this results in some hardware being\r
  // detected multiple times. We work around this by faking absent\r
  // devices\r
  if ((EfiPciAddress->Bus == 0) && ((EfiPciAddress->Device != 0) || (EfiPciAddress->Function != 0))) {\r
    *((UINT32 *)Buffer) = 0xffffffff;\r
    return EFI_SUCCESS;\r
  }\r
  if ((EfiPciAddress->Bus == 1) && ((EfiPciAddress->Device != 0) || (EfiPciAddress->Function != 0))) {\r
    *((UINT32 *)Buffer) = 0xffffffff;\r
    return EFI_SUCCESS;\r
  }\r
\r
  // Work around incorrect class ID in the root bridge\r
  if ((EfiPciAddress->Bus == 0) && (EfiPciAddress->Device == 0) && (EfiPciAddress->Function == 0) && (Offset == 8)) {\r
    *((UINT32 *)Buffer) = 0x06040001;\r
    return EFI_SUCCESS;\r
   }\r
\r
  Address = PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) |\r
                         (EfiPciAddress->Device << 15) |\r
                         (EfiPciAddress->Function << 12) | Offset);\r
\r
  if ((Address < PCI_ECAM_BASE) || (Address > PCI_ECAM_BASE + PCI_ECAM_SIZE)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
PciRbPciWrite (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   EfiAddress,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  )\r
{\r
  UINT32                      Offset;\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
  EFI_CPU_IO2_PROTOCOL        *CpuIo;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;\r
  UINT64                      Address;\r
\r
  EfiPciAddress  = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
  CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance);\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (EfiPciAddress->ExtendedRegister)\r
    Offset = EfiPciAddress->ExtendedRegister;\r
  else\r
    Offset = EfiPciAddress->Register;\r
\r
  Address = PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) |\r
                         (EfiPciAddress->Device << 15) |\r
                         (EfiPciAddress->Function << 12) | Offset);\r
\r
  if (Address < PCI_ECAM_BASE || Address > PCI_ECAM_BASE + PCI_ECAM_SIZE) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
PciRbCopyMem (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   DestAddress,\r
  IN     UINT64                                   SrcAddress,\r
  IN     UINTN                                    Count\r
  )\r
{\r
  EFI_STATUS  Status;\r
  BOOLEAN     Direction;\r
  UINTN       Stride;\r
  UINTN       Index;\r
  UINT64      Result;\r
\r
  PCI_TRACE ("PciRbCopyMem()");\r
\r
  if (Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (DestAddress == SrcAddress) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  Stride = (UINTN)(1 << Width);\r
\r
  Direction = TRUE;\r
  if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
    Direction   = FALSE;\r
    SrcAddress  = SrcAddress  + (Count-1) * Stride;\r
    DestAddress = DestAddress + (Count-1) * Stride;\r
  }\r
\r
  for (Index = 0; Index < Count; Index++) {\r
    Status = PciRbMemRead (\r
               This,\r
               Width,\r
               SrcAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    Status = PciRbMemWrite (\r
               This,\r
               Width,\r
               DestAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    if (Direction) {\r
      SrcAddress  += Stride;\r
      DestAddress += Stride;\r
    } else {\r
      SrcAddress  -= Stride;\r
      DestAddress -= Stride;\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbMap (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  )\r
{\r
  DMA_MAP_OPERATION   DmaOperation;\r
\r
  PCI_TRACE ("PciRbMap()");\r
\r
  if (Operation == EfiPciOperationBusMasterRead ||\r
      Operation == EfiPciOperationBusMasterRead64) {\r
    DmaOperation = MapOperationBusMasterRead;\r
  } else if (Operation == EfiPciOperationBusMasterWrite ||\r
             Operation == EfiPciOperationBusMasterWrite64) {\r
    DmaOperation = MapOperationBusMasterWrite;\r
  } else if (Operation == EfiPciOperationBusMasterCommonBuffer ||\r
             Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
    DmaOperation = MapOperationBusMasterCommonBuffer;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);\r
}\r
\r
EFI_STATUS\r
PciRbUnMap (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  VOID                                     *Mapping\r
  )\r
{\r
  PCI_TRACE ("PciRbUnMap()");\r
  return DmaUnmap (Mapping);\r
}\r
\r
EFI_STATUS\r
PciRbAllocateBuffer (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_ALLOCATE_TYPE                        Type,\r
  IN     EFI_MEMORY_TYPE                          MemoryType,\r
  IN     UINTN                                    Pages,\r
  IN OUT VOID                                     **HostAddress,\r
  IN     UINT64                                   Attributes\r
  )\r
{\r
  PCI_TRACE ("PciRbAllocateBuffer()");\r
\r
  if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);\r
}\r
\r
EFI_STATUS\r
PciRbFreeBuffer (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  UINTN                                    Pages,\r
  IN  VOID                                     *HostAddress\r
  )\r
{\r
  PCI_TRACE ("PciRbFreeBuffer()");\r
  return DmaFreeBuffer (Pages, HostAddress);\r
}\r
\r
EFI_STATUS\r
PciRbFlush (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
  )\r
{\r
  PCI_TRACE ("PciRbFlush()");\r
\r
  //TODO: Not supported yet\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbSetAttributes (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     UINT64                                   Attributes,\r
  IN OUT UINT64                                   *ResourceBase,\r
  IN OUT UINT64                                   *ResourceLength\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
\r
  PCI_TRACE ("PciRbSetAttributes()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
\r
  if (Attributes) {\r
    if ((Attributes & (~(RootBridgeInstance->Supports))) != 0) {\r
      return EFI_UNSUPPORTED;\r
    }\r
  }\r
\r
  //TODO: Cannot allowed to change attributes\r
  if (Attributes & ~RootBridgeInstance->Attributes) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbGetAttributes (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  OUT UINT64                                   *Supported,\r
  OUT UINT64                                   *Attributes\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE    *RootBridgeInstance;\r
\r
  PCI_TRACE ("PciRbGetAttributes()");\r
\r
  RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
\r
  if (Attributes == NULL && Supported == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  // Set the return value for Supported and Attributes\r
  if (Supported) {\r
    *Supported  = RootBridgeInstance->Supports;\r
  }\r
\r
  if (Attributes) {\r
    *Attributes = RootBridgeInstance->Attributes;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbConfiguration (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL          *This,\r
  OUT VOID                                     **Resources\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE              *RootBridge;\r
  UINTN                                 Index;\r
\r
  PCI_TRACE ("PciRbConfiguration()");\r
\r
  RootBridge = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This);\r
\r
  for (Index = 0; Index < ResTypeMax; Index++) {\r
    //if (ResAlloc[Index].Length != 0) => Resource allocated\r
    if (RootBridge->ResAlloc[Index].Length != 0) {\r
      Configuration.SpaceDesp[Index].AddrRangeMin = RootBridge->ResAlloc[Index].Base;\r
      Configuration.SpaceDesp[Index].AddrRangeMax = RootBridge->ResAlloc[Index].Base + RootBridge->ResAlloc[Index].Length - 1;\r
      Configuration.SpaceDesp[Index].AddrLen      = RootBridge->ResAlloc[Index].Length;\r
    }\r
  }\r
\r
  // Set up Configuration for the bus\r
  Configuration.SpaceDesp[Index].AddrRangeMin = RootBridge->BusStart;\r
  Configuration.SpaceDesp[Index].AddrLen      = RootBridge->BusLength;\r
\r
  *Resources = &Configuration;\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbConstructor (\r
  IN  PCI_HOST_BRIDGE_INSTANCE *HostBridge,\r
  IN  UINT32 PciAcpiUid,\r
  IN  UINT64 MemAllocAttributes\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE* RootBridge;\r
  EFI_STATUS Status;\r
\r
  PCI_TRACE ("PciRbConstructor()");\r
\r
  // Allocate Memory for the Instance from a Template\r
  RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));\r
  if (RootBridge == NULL) {\r
    PCI_TRACE ("PciRbConstructor(): ERROR: Out of Resources");\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
  CopyMem (&(RootBridge->DevicePath), &gDevicePathTemplate, sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH));\r
  CopyMem (&(RootBridge->Io), &gIoTemplate, sizeof (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL));\r
\r
  // Set Parent Handle\r
  RootBridge->Io.ParentHandle = HostBridge->Handle;\r
\r
  // Attach the Root Bridge to the PCI Host Bridge Instance\r
  RootBridge->HostBridge = HostBridge;\r
\r
  // Set Device Path for this Root Bridge\r
  RootBridge->DevicePath.Acpi.UID = PciAcpiUid;\r
\r
  RootBridge->BusStart  = FixedPcdGet32 (PcdPciBusMin);\r
  RootBridge->BusLength = FixedPcdGet32 (PcdPciBusMax) - FixedPcdGet32 (PcdPciBusMin) + 1;\r
\r
  // PCI Attributes\r
  RootBridge->Supports = 0;\r
  RootBridge->Attributes = 0;\r
\r
  // Install Protocol Instances. It will also generate a device handle for the PCI Root Bridge\r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                      &RootBridge->Handle,\r
                      &gEfiDevicePathProtocolGuid, &RootBridge->DevicePath,\r
                      &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io,\r
                      NULL\r
                      );\r
  ASSERT (RootBridge->Signature == PCI_ROOT_BRIDGE_SIGNATURE);\r
  if (EFI_ERROR (Status)) {\r
    PCI_TRACE ("PciRbConstructor(): ERROR: Fail to install Protocol Interfaces");\r
    FreePool (RootBridge);\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  HostBridge->RootBridge = RootBridge;\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciRbDestructor (\r
  IN  PCI_ROOT_BRIDGE_INSTANCE* RootBridge\r
  )\r
{\r
  EFI_STATUS Status;\r
\r
  Status = gBS->UninstallMultipleProtocolInterfaces (\r
                        RootBridge->Handle,\r
                        &gEfiDevicePathProtocolGuid, &RootBridge->DevicePath,\r
                        &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io,\r
                        NULL\r
                        );\r
\r
  FreePool (RootBridge);\r
\r
  return Status;\r
}\r