ArmPlatformPkg/ArmJuno: fix Juno PIO host bridge mapping

[mirror_edk2.git] / ArmPlatformPkg / ArmJunoPkg / Drivers / PciHostBridgeDxe / XPressRich3.c

/** @file\r
*  Initialize the XPress-RICH3 PCIe Root complex\r
*\r
*  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include "PciHostBridge.h"\r
\r
#include <Protocol/Cpu.h>\r
\r
#include "ArmPlatform.h"\r
\r
EFI_CPU_ARCH_PROTOCOL   *mCpu;\r
\r
#define PCI_BRIDGE_REVISION_ID                        1\r
#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf)  ((Class << 16) | (SubClass << 8) | ProgIf)\r
#define PLDA_BRIDGE_CCR                               CLASS_CODE_REGISTER(PCI_CLASS_BRIDGE, \\r
                                                                          PCI_CLASS_BRIDGE_P2P, \\r
                                                                          PCI_IF_BRIDGE_P2P)\r
\r
STATIC\r
VOID\r
SetTranslationAddressEntry (\r
  IN  EFI_CPU_IO2_PROTOCOL *CpuIo,\r
  IN UINTN                  Entry,\r
  IN UINT64                 SourceAddress,\r
  IN UINT64                 TranslatedAddress,\r
  IN UINT64                 TranslationSize,\r
  IN UINT64                 TranslationParameter\r
  )\r
{\r
  UINTN Log2Size = HighBitSet64 (TranslationSize);\r
\r
  // Ensure the size is a power of two. Restriction form the AXI Translation logic\r
  // Othwerwise we increase the translation size\r
  if (TranslationSize != (1ULL << Log2Size)) {\r
    DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been increased to "\r
                        "be a power of two for the AXI translation table.\n",\r
                        TranslationSize, SourceAddress));\r
    Log2Size++;\r
  }\r
\r
  PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE,\r
      (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1);\r
  PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32);\r
\r
  PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)TranslatedAddress);\r
  PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >> 32);\r
\r
  PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter);\r
}\r
\r
EFI_STATUS\r
HWPciRbInit (\r
  IN  EFI_CPU_IO2_PROTOCOL *CpuIo\r
  )\r
{\r
  UINT32 Value;\r
  UINT32 Index;\r
  UINTN  TranslationTable;\r
\r
  PCI_TRACE ("VExpressPciRbInit()");\r
\r
  PCI_TRACE ("PCIe Setting up Address Translation");\r
\r
  // The Juno PIO window is 8M, so we need full 32-bit PIO decoding.\r
  PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 |\r
                         PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);\r
\r
  // Setup the PCI Configuration Registers\r
  // Offset 0a: SubClass       04 PCI-PCI Bridge\r
  // Offset 0b: BaseClass      06 Bridge Device\r
  // The Class Code register is a 24 bit and can be configured by setting up the PCIE_PCI_IDS\r
  // Refer [1] Chapter 13\r
  PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID));\r
\r
  //\r
  // PCIE Window 0 -> AXI4 Slave 0 Address Translations\r
  //\r
  TranslationTable = VEXPRESS_ATR_PCIE_WIN0;\r
\r
  // MSI Support\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_BASE, ARM_JUNO_GIV2M_MSI_BASE,\r
      ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE);\r
  TranslationTable += PCI_ATR_ENTRY_SIZE;\r
\r
  // System Memory Support\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase),\r
      PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY);\r
  TranslationTable += PCI_ATR_ENTRY_SIZE;\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,\r
      ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY);\r
\r
  //\r
  // PCIE Window 0 -> AXI4 Slave 0 Address Translations\r
  //\r
  TranslationTable = VEXPRESS_ATR_AXI4_SLV1;\r
\r
  // PCI ECAM Support\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF);\r
  TranslationTable += PCI_ATR_ENTRY_SIZE;\r
\r
  // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0\r
  // AKA, PIO addresses used by endpoints are generally in the range of 0-64K.\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);\r
  TranslationTable += PCI_ATR_ENTRY_SIZE;\r
\r
  // PCI MEM32 Support\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI_MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY);\r
  TranslationTable += PCI_ATR_ENTRY_SIZE;\r
\r
  // PCI MEM64 Support\r
  SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI_MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY);\r
\r
  // Add credits\r
  PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818);\r
  PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1);\r
\r
  // Allow ECRC\r
  PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006);\r
\r
  // Reset controller\r
  PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_REL);\r
\r
  // Wait for reset\r
  for (Index = 0; Index < 1000; Index++) {\r
    gBS->Stall (1000);\r
    PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value);\r
    if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) == PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) {\r
      break;\r
    }\r
  }\r
\r
  // Check for reset\r
  if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) {\r
    DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value));\r
    return EFI_NOT_READY;\r
  }\r
\r
  gBS->Stall (1000);\r
  PCI_TRACE ("Checking link Status...");\r
\r
  // Wait for Link Up\r
  for (Index = 0; Index < 1000; Index++) {\r
    gBS->Stall (1000);\r
    PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value);\r
    if (Value & LINK_UP) {\r
      break;\r
    }\r
  }\r
\r
  // Check for link up\r
  if (!(Value & LINK_UP)) {\r
    DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value));\r
    return EFI_NOT_READY;\r
  }\r
\r
  PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx);\r
\r
  return EFI_SUCCESS;\r
}\r