projects / mirror_edk2.git / blame
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|---|---|---|
| 9f38945f OM |
1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r | |
| 4 | *\r | |
| 5 | * This program and the accompanying materials\r | |
| 6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | * which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | * http://opensource.org/licenses/bsd-license.php\r | |
| 9 | *\r | |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | *\r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __ARM_JUNO_H__\r | |
| 16 | #define __ARM_JUNO_H__\r | |
| 17 | \r | |
| 18 | #include <VExpressMotherBoard.h>\r | |
| 19 | \r | |
| 20 | /***********************************************************************************\r | |
| 21 | // Platform Memory Map\r | |
| 22 | ************************************************************************************/\r | |
| 23 | \r | |
| 24 | // Motherboard Peripheral and On-chip peripheral\r | |
| 25 | #define ARM_VE_BOARD_PERIPH_BASE 0x1C010000\r | |
| 7ac29b54 JL |
26 | #define ARM_VE_BOARD_SYS_ID 0x0000\r |
| 27 | #define ARM_VE_BOARD_SYS_PCIE_GBE_L 0x0074\r | |
| 28 | #define ARM_VE_BOARD_SYS_PCIE_GBE_H 0x0078\r | |
| 29 | \r | |
| 30 | #define ARM_VE_BOARD_SYS_ID_REV(word) ((word >> 28) & 0xff)\r | |
| 9f38945f OM |
31 | \r |
| 32 | // NOR Flash 0\r | |
| 33 | #define ARM_VE_SMB_NOR0_BASE 0x08000000\r | |
| 34 | #define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r | |
| 35 | \r | |
| 36 | // Off-Chip peripherals (USB, Ethernet, VRAM)\r | |
| 37 | #define ARM_VE_SMB_PERIPH_BASE 0x18000000\r | |
| 38 | #define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)\r | |
| 39 | \r | |
| 40 | // On-Chip non-secure ROM\r | |
| 41 | #define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000\r | |
| 42 | #define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB\r | |
| 43 | \r | |
| 44 | // On-Chip Peripherals\r | |
| 45 | #define ARM_JUNO_PERIPHERALS_BASE 0x20000000\r | |
| 46 | #define ARM_JUNO_PERIPHERALS_SZ 0x0E000000\r | |
| 47 | \r | |
| efcc052b | 48 | // PCIe MSI address window\r |
| 1bb1f35f OM |
49 | #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000\r |
| 50 | #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB\r | |
| 51 | \r | |
| efcc052b JL |
52 | // PCIe MSI to SPI mapping range\r |
| 53 | #define ARM_JUNO_GIV2M_MSI_SPI_BASE 224\r | |
| 54 | #define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127\r | |
| 55 | \r | |
| 9f38945f OM |
56 | // On-Chip non-secure SRAM\r |
| 57 | #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000\r | |
| 58 | #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB\r | |
| 59 | \r | |
| 60 | // SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)\r | |
| 61 | #define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000\r | |
| 62 | #define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)\r | |
| 63 | \r | |
| 64 | // 6GB of DRAM from the 64bit address space\r | |
| 65 | #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000\r | |
| 66 | #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)\r | |
| 67 | \r | |
| 3399d5be OM |
68 | //\r |
| 69 | // ACPI table information used to initialize tables.\r | |
| 70 | //\r | |
| 71 | #define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long\r | |
| 72 | #define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long\r | |
| 73 | #define EFI_ACPI_ARM_OEM_REVISION 0x20140727\r | |
| 74 | #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')\r | |
| 75 | #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099\r | |
| 76 | \r | |
| 77 | // A macro to initialise the common header part of EFI ACPI tables as defined by\r | |
| 78 | // EFI_ACPI_DESCRIPTION_HEADER structure.\r | |
| 79 | #define ARM_ACPI_HEADER(Signature, Type, Revision) { \\r | |
| 80 | Signature, /* UINT32 Signature */ \\r | |
| 81 | sizeof (Type), /* UINT32 Length */ \\r | |
| 82 | Revision, /* UINT8 Revision */ \\r | |
| 83 | 0, /* UINT8 Checksum */ \\r | |
| 84 | { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \\r | |
| 85 | EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \\r | |
| 86 | EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \\r | |
| 87 | EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \\r | |
| 88 | EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \\r | |
| 89 | }\r | |
| 90 | \r | |
| 7ac29b54 JL |
91 | //\r |
| 92 | // Hardware platform identifiers\r | |
| 93 | //\r | |
| 94 | #define JUNO_REVISION_PROTOTYPE 0\r | |
| 95 | #define JUNO_REVISION_R0 1\r | |
| 96 | #define JUNO_REVISION_R1 2\r | |
| 97 | #define JUNO_REVISION_R2 3\r | |
| 98 | #define JUNO_REVISION_UKNOWN 0xFF\r | |
| 99 | \r | |
| 100 | //\r | |
| 101 | // We detect whether we are running on a Juno r0, r1 or r2\r | |
| 102 | // board at runtime by checking the value of board SYS_ID\r | |
| 103 | //\r | |
| 104 | #define GetJunoRevision(JunoRevision) \\r | |
| 105 | { \\r | |
| 106 | UINT32 SysId; \\r | |
| 107 | SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \\r | |
| 108 | JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \\r | |
| 109 | }\r | |
| 110 | \r | |
| 2596e61a OM |
111 | #define JUNO_WATCHDOG_COUNT 2\r |
| 112 | \r | |
| 113 | // Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest\r | |
| 114 | //#define ARM_JUNO_ACPI_5_0\r | |
| 115 | \r | |
| c1fee786 RC |
116 | //\r |
| 117 | // Address of the system registers that contain the MAC address\r | |
| 118 | // assigned to the PCI Gigabyte Ethernet device.\r | |
| 119 | //\r | |
| 120 | \r | |
| 7ac29b54 JL |
121 | #define ARM_JUNO_SYS_PCIGBE_L (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)\r |
| 122 | #define ARM_JUNO_SYS_PCIGBE_H (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)\r | |
| c1fee786 | 123 | \r |
| 9f38945f | 124 | #endif\r |