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1d5d0ae9 1/** @file
2*
3* Copyright (c) 2011, ARM Limited. All rights reserved.
4*
5* This program and the accompanying materials
6* are licensed and made available under the terms and conditions of the BSD License
7* which accompanies this distribution. The full text of the license may be found at
8* http://opensource.org/licenses/bsd-license.php
9*
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12*
13**/
14
15#include <Library/IoLib.h>
16#include <Library/ArmPlatformLib.h>
17#include <Library/DebugLib.h>
18#include <Library/PcdLib.h>
23792dea 19
1d5d0ae9 20#include <Drivers/PL341Dmc.h>
23792dea 21#include <Drivers/SP804Timer.h>
1d5d0ae9 22
44788bae 23#include <Ppi/ArmMpCoreInfo.h>
24
5cc45b70 25#include <ArmPlatform.h>
26
44788bae 27ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {
28 {
29 // Cluster 0, Core 0
30 0x0, 0x0,
31
32 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
33 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
34 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
35 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
36 (UINT64)0xFFFFFFFF
37 },
38 {
39 // Cluster 0, Core 1
40 0x0, 0x1,
41
42 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
43 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
44 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
45 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
46 (UINT64)0xFFFFFFFF
47 }
48};
49
1d5d0ae9 50/**
51 Return if Trustzone is supported by your platform
52
53 A non-zero value must be returned if you want to support a Secure World on your platform.
54 ArmPlatformTrustzoneInit() will later set up the secure regions.
55 This function can return 0 even if Trustzone is supported by your processor. In this case,
56 the platform will continue to run in Secure World.
57
58 @return A non-zero value if Trustzone supported.
59
60**/
aa01abaa 61UINTN
62ArmPlatformTrustzoneSupported (
63 VOID
64 )
65{
1d5d0ae9 66 // There is no Trustzone controllers (TZPC & TZASC) and no Secure Memory on RTSM
aa01abaa 67 return FALSE;
1d5d0ae9 68}
69
1d5d0ae9 70/**
71 Remap the memory at 0x0
72
73 Some platform requires or gives the ability to remap the memory at the address 0x0.
74 This function can do nothing if this feature is not relevant to your platform.
75
76**/
aa01abaa 77VOID
78ArmPlatformBootRemapping (
79 VOID
80 )
81{
1d5d0ae9 82 // Disable memory remapping and return to normal mapping
aa01abaa 83 MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
1d5d0ae9 84}
85
a534d714 86/**
87 Return the current Boot Mode
88
89 This function returns the boot reason on the platform
90
91**/
92EFI_BOOT_MODE
93ArmPlatformGetBootMode (
94 VOID
95 )
96{
97 return BOOT_WITH_FULL_CONFIGURATION;
98}
99
aa01abaa 100/**
101 Initialize controllers that must setup in the normal world
102
5cc45b70 103 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
aa01abaa 104 in the PEI phase.
105
106**/
107VOID
108ArmPlatformNormalInitialize (
109 VOID
110 )
111{
23792dea 112 // Configure periodic timer (TIMER0) for 1MHz operation
113 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
114 // Configure 1MHz clock
115 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
116 // configure SP810 to use 1MHz clock and disable
117 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
118 // Configure SP810 to use 1MHz clock and disable
119 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
aa01abaa 120}
121
1d5d0ae9 122/**
123 Initialize the system (or sometimes called permanent) memory
124
125 This memory is generally represented by the DRAM.
126
127**/
aa01abaa 128VOID
129ArmPlatformInitializeSystemMemory (
130 VOID
131 )
132{
133 // We do not need to initialize the System Memory on RTSM
1d5d0ae9 134}
44788bae 135
136EFI_STATUS
137PrePeiCoreGetMpCoreInfo (
138 OUT UINTN *CoreCount,
139 OUT ARM_CORE_INFO **ArmCoreTable
140 )
141{
142 if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {
143 *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
144 *ArmCoreTable = mRealViewEbMpCoreInfoTable;
145 return EFI_SUCCESS;
146 } else {
147 return EFI_UNSUPPORTED;
148 }
149}
150
151// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
152EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
153ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
154
155EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
156 {
157 EFI_PEI_PPI_DESCRIPTOR_PPI,
158 &mArmMpCoreInfoPpiGuid,
159 &mMpCoreInfoPpi
160 }
161};
162
77de7e53 163VOID
164ArmPlatformGetPlatformPpiList (
165 OUT UINTN *PpiListSize,
166 OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
167 )
168{
44788bae 169 *PpiListSize = sizeof(gPlatformPpiTable);
170 *PpiList = gPlatformPpiTable;
77de7e53 171}
172