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1e57a462 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/IoLib.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/ArmPlatformLib.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | \r | |
21 | #include <Drivers/PL341Dmc.h>\r | |
22 | #include <Drivers/SP804Timer.h>\r | |
23 | \r | |
24 | #include <Ppi/ArmMpCoreInfo.h>\r | |
25 | \r | |
26 | #include <ArmPlatform.h>\r | |
27 | \r | |
28 | ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {\r | |
29 | {\r | |
30 | // Cluster 0, Core 0\r | |
31 | 0x0, 0x0,\r | |
32 | \r | |
33 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
34 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,\r | |
35 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,\r | |
36 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,\r | |
37 | (UINT64)0xFFFFFFFF\r | |
38 | },\r | |
39 | {\r | |
40 | // Cluster 0, Core 1\r | |
41 | 0x0, 0x1,\r | |
42 | \r | |
43 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r | |
44 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,\r | |
45 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,\r | |
46 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,\r | |
47 | (UINT64)0xFFFFFFFF\r | |
48 | }\r | |
49 | };\r | |
50 | \r | |
51 | /**\r | |
52 | Return the current Boot Mode\r | |
53 | \r | |
54 | This function returns the boot reason on the platform\r | |
55 | \r | |
56 | **/\r | |
57 | EFI_BOOT_MODE\r | |
58 | ArmPlatformGetBootMode (\r | |
59 | VOID\r | |
60 | )\r | |
61 | {\r | |
62 | return BOOT_WITH_FULL_CONFIGURATION;\r | |
63 | }\r | |
64 | \r | |
65 | /**\r | |
66 | Initialize controllers that must setup in the normal world\r | |
67 | \r | |
68 | This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r | |
69 | in the PEI phase.\r | |
70 | \r | |
71 | **/\r | |
72 | RETURN_STATUS\r | |
73 | ArmPlatformInitialize (\r | |
74 | IN UINTN MpId\r | |
75 | )\r | |
76 | {\r | |
77 | if (!IS_PRIMARY_CORE(MpId)) {\r | |
78 | return RETURN_SUCCESS;\r | |
79 | }\r | |
80 | \r | |
81 | // Disable memory remapping and return to normal mapping\r | |
82 | MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE\r | |
83 | \r | |
84 | // Configure periodic timer (TIMER0) for 1MHz operation\r | |
85 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r | |
86 | // Configure 1MHz clock\r | |
87 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r | |
88 | // configure SP810 to use 1MHz clock and disable\r | |
89 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r | |
90 | // Configure SP810 to use 1MHz clock and disable\r | |
91 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r | |
92 | \r | |
93 | return RETURN_SUCCESS;\r | |
94 | }\r | |
95 | \r | |
96 | /**\r | |
97 | Initialize the system (or sometimes called permanent) memory\r | |
98 | \r | |
99 | This memory is generally represented by the DRAM.\r | |
100 | \r | |
101 | **/\r | |
102 | VOID\r | |
103 | ArmPlatformInitializeSystemMemory (\r | |
104 | VOID\r | |
105 | )\r | |
106 | {\r | |
107 | // We do not need to initialize the System Memory on RTSM\r | |
108 | }\r | |
109 | \r | |
110 | EFI_STATUS\r | |
111 | PrePeiCoreGetMpCoreInfo (\r | |
112 | OUT UINTN *CoreCount,\r | |
113 | OUT ARM_CORE_INFO **ArmCoreTable\r | |
114 | )\r | |
115 | {\r | |
116 | if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {\r | |
117 | *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);\r | |
118 | *ArmCoreTable = mRealViewEbMpCoreInfoTable;\r | |
119 | return EFI_SUCCESS;\r | |
120 | } else {\r | |
121 | return EFI_UNSUPPORTED;\r | |
122 | }\r | |
123 | }\r | |
124 | \r | |
125 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r | |
126 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r | |
127 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r | |
128 | \r | |
129 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r | |
130 | {\r | |
131 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r | |
132 | &mArmMpCoreInfoPpiGuid,\r | |
133 | &mMpCoreInfoPpi\r | |
134 | }\r | |
135 | };\r | |
136 | \r | |
137 | VOID\r | |
138 | ArmPlatformGetPlatformPpiList (\r | |
139 | OUT UINTN *PpiListSize,\r | |
140 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
141 | )\r | |
142 | {\r | |
143 | *PpiListSize = sizeof(gPlatformPpiTable);\r | |
144 | *PpiList = gPlatformPpiTable;\r | |
145 | }\r | |
146 | \r |