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1 | /** @file\r |
| 2 | * Header defining Versatile Express constants (Base addresses, sizes, flags)\r |
| 3 | *\r |
| 4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 5 | *\r |
| 6 | * This program and the accompanying materials\r |
| 7 | * are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | * which accompanies this distribution. The full text of the license may be found at\r |
| 9 | * http://opensource.org/licenses/bsd-license.php\r |
| 10 | *\r |
| 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | *\r |
| 14 | **/\r |
| 15 | \r |
| 16 | #ifndef __VEXPRESSMOTHERBOARD_H_\r |
| 17 | #define __VEXPRESSMOTHERBOARD_H_\r |
| 18 | \r |
| 19 | #include <ArmPlatform.h>\r |
| 20 | \r |
| 21 | /***********************************************************************************\r |
| 22 | // Motherboard memory-mapped peripherals\r |
| 23 | ************************************************************************************/\r |
| 24 | \r |
| 25 | // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r |
| 26 | #define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)\r |
| 27 | #define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r |
| 28 | #define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r |
| 29 | #define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r |
| 30 | #define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r |
| 31 | #define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r |
| 32 | #define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r |
| 33 | #define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)\r |
| 34 | #define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r |
| 35 | #define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r |
| 36 | #define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r |
| 37 | #define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r |
| 38 | #define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r |
| 39 | \r |
| 40 | // SP810 Controller\r |
| 41 | #define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r |
| 42 | \r |
| 43 | // Uart0\r |
| 44 | #define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r |
| 45 | \r |
| 46 | // SP805 Watchdog on motherboard\r |
| 47 | #define SP805_WDOG_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)\r |
| 48 | \r |
| 49 | // SP804 Timer Bases\r |
| 50 | #define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r |
| 51 | #define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r |
| 52 | #define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r |
| 53 | #define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r |
| 54 | \r |
| 55 | // PL031 Real Time Clock\r |
| 56 | #define PL031_RTC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x17000)\r |
| 57 | \r |
| 58 | // PL111 Colour LCD Controller - motherboard\r |
| 59 | #define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)\r |
| 60 | #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1\r |
| 61 | \r |
| 62 | // VRAM offset for the PL111 Colour LCD Controller on the motherboard\r |
| 63 | #define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r |
| 64 | \r |
| 65 | #define SYS_PROC_ID_UNSUPPORTED 0xFF\r |
| 66 | #define SYS_PROC_ID_CORTEX_A9 0x0C\r |
| 67 | \r |
| 68 | //\r |
| 69 | // Sites where the peripheral is fitted\r |
| 70 | //\r |
| 71 | #define ARM_VE_UNSUPPORTED ~0\r |
| 72 | #define ARM_VE_MOTHERBOARD_SITE 0\r |
| 73 | #define ARM_VE_DAUGHTERBOARD_1_SITE 1\r |
| 74 | #define ARM_VE_DAUGHTERBOARD_2_SITE 2\r |
| 75 | \r |
| 76 | #endif /* VEXPRESSMOTHERBOARD_H_ */\r |
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